Understanding fundamental design choices in single-ISA heterogeneous multicore architectures

Abstract

Single-ISA heterogeneous multicore processors have gained substantial interest over the past few years because of their power efficiency, as they offer the potential for high overall chip throughput within a given power budget. Prior work in heterogeneous architectures has mainly focused on how heterogeneity can improve overall system throughput. To what extent heterogeneity affects per-program performance has remained largely unanswered. In this article, we aim at understanding how heterogeneity affects both chip throughput and per-program performance; how heterogeneous architectures compare to homogeneous architectures under both performance metrics; and how fundamental design choices, such as core type, cache size, and off-chip bandwidth, affect performance.We use analytical modeling to explore a large space of single-ISA heterogeneous architectures. The analytical model has linear-time complexity in the number of core types and programs of interest, and offers a unique opportunity for exploring the large space of both homogeneous and heterogeneous multicore processors in limited time. Our analysis provides several interesting insights: While it is true that heterogeneity can improve system throughput, it fundamentally trades per-program performance for chip throughput; although some heterogeneous configurations yield better throughput and per-program performance than homogeneous designs, some homogeneous configurations are optimal for particular throughput versus perprogram performance trade-offs. Two core types provide most of the benefits from heterogeneity and a larger number of core types does not contribute much; job-to-core mapping is both important and challenging for heterogeneous multicore processors to achieve optimum performance. Limited off-chip bandwidth does alter some of the fundamental design choices in heterogeneous multicore architectures, such as the need for large on-chip caches for achieving high throughput, and per-program performance degrading more relative to throughput under constrained off-chip bandwidth.

DyScale: A MapReduce Job Scheduler for Heterogeneous Multicore Processors

“…These proposed techniques focus on improving the overall chip-level throughput. The work in [21] explores the per-program performance in addition to the overall chip level throughput when using heterogeneous multi-core processors.…”

Heterogeneous architecture design with emerging 3D and non-volatile memory technologies

“…Moreover, since the application requirement changes along the execution phases, it is necessary for dynamic application mapping and migration. Recently, substantial research efforts are made to accurately model the application performance under different cores [9] and conduct application mapping/scheduling and migration [10,11,12]. An analytical performance model is used and the fundamental design tradeoffs of single-ISA heterogeneous multi-core is studied [9].…”

Heterogeneity-conscious parallel query execution

“…Such architectures include ARM's big.LITTLE [23] and Intel's QuickIA [6], which combines a Xeon server CPU with an energy efficient Atom CPU in a single system. Previous work on single-ISA heterogeneous architectures has shown that database systems need to be adapted in order to optimally use heterogeneous processors [3] and that job-to-core mapping in such a setting is important and challenging [29].…”

“…Although multi-core scaling helps to alleviate dark silicon, it is just a workaround as the fraction of transistors that can be powered continues to decrease with each process generation [2]. Future processors will thus need to become more heterogeneous, i.e., be composed of cores with asymmetric performance and power characteristics to use transistors effectively [2,7,8,29].…”

“…just like non-uniform memory access (NUMA) needs to be taken into account during query processing [17,16], we argue that processor heterogeneity needs to be exposed to the database system [3] in order to achieve an optimal job-to-core mapping. Such a mapping is both important and challenging: heuristics based on load, CPI, and miss rates do not achieve optimum performance and energy efficiency [29,3]. Whereas the operating system and compilers rely on such heuristics, database systems have a priori knowledge about the workload, enabling them to make better mapping decisions.…”