2013
DOI: 10.1016/j.mee.2013.03.008
|View full text |Cite
|
Sign up to set email alerts
|

Understanding Ge impact on VT and VFB in Si1−xGex/Si pMOSFETs

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1
1
1

Citation Types

4
3
0

Year Published

2013
2013
2021
2021

Publication Types

Select...
4
2

Relationship

2
4

Authors

Journals

citations
Cited by 8 publications
(7 citation statements)
references
References 4 publications
4
3
0
Order By: Relevance
“…Match is obtained for pure Si whereas an additional lS0mV shift is needed to reproduce the experimental VT and VFB parameters of the Sio7Geo 3 pMOS. This discrepancy is close to the shift obtained in [7] using conventional VFB extraction technique (see [7] for more details. ), proving the validity of the split CV extraction technique.…”
Section: Measurements Of the Srge/sr Pmosfetssupporting
confidence: 88%
See 1 more Smart Citation
“…Match is obtained for pure Si whereas an additional lS0mV shift is needed to reproduce the experimental VT and VFB parameters of the Sio7Geo 3 pMOS. This discrepancy is close to the shift obtained in [7] using conventional VFB extraction technique (see [7] for more details. ), proving the validity of the split CV extraction technique.…”
Section: Measurements Of the Srge/sr Pmosfetssupporting
confidence: 88%
“…7Geo . iSi pMOS is found in good agreement with the VT obtained by the extraction method explained in [7]. The VT@40% of C m a…”
Section: Simulation Modelssupporting
confidence: 84%
“…The meaningful results provided by the first-principle Ab-initio calculations reported in [7] complement well the cSiGe WF k.p calculations of [6] that account for quantization effects with Vg and Tsi. In-line characterization techniques based on x-ray diffraction (XRD) combined with TCAD simulations are currently in development to determine the WF.…”
Section: A Modeling Of the Gate Stacksupporting
confidence: 68%
“…Adjustment of EOT and metal work function (WF eff ) of simulated structure is done to fit experiment, enabling a reliable extraction of EOT, VT and flat band voltage (VFB) (Fig.2b). VFB corresponds to the gate bias at zero substrate charge and VT is estimated from 40% of C max,inv [6]. EOT has been measured for the three different pMOS.…”
Section: Modelingmentioning
confidence: 99%