Understanding MOSFET mismatch for analog design

Abstract

This paper addresses misconceptions about MOS-FET mismatch for analog desi . V, mismatch does not follow a simplistic 1/( s " area) law, especially for widelshort and narrowllong devices, which are common geometries in analog circuits. Further, V, and gain factor are not appropriate parameters for modeling mismatch. A physically based mismatch model can be used to obtain dramatic improvements in prediction of mismatch. This model is applied to MOS-FET current mirrors to show some non-obvious effects over bias, geometry, and multiple unit devices.

Robust focal-plane analog processing hardware for dynamic texture segmentation

“…Typical mean conditions were used, introducing independent Gaussian deviations of W , L, µ 0 and t ox with σ = 10%. These deviations generate in turn deviations in the crucial parameters V th , γ and β [7] which directly affect the previously described equations defining the processing. The results are summarized in Table II.…”

ALAMO: An Improved σ - Space Based Methodology for Modeling Process Parameter Variations in Analog Circuits

“…Global variation does not related to circuit layout and device sizes, while local variation does [6,8].…”

“…A common limitation of both alternatives is that they consider only parasitic without tackling other layout aspects, e.g., process parameter variations, mismatching, thermal effects and substrate coupling. Especially for deep submicron (DSM) design, process variations are arguably as critical as parasitic, and ought to be considered early in the design flow [6].…”

Series-parallel association of transistors for the reduction of random offset in non-unity gain current mirrors

“…An equation equivalent to (6) can be derived for ∆β i variations in series transistors. Variations in β and V T , in parallel transistors are calculated as in (3). The normalized mismatch current standard deviation is obtained: …”

“…For the sake of simplicity, only variations in V T and β -as in (1)-will be considered in this paper. Nevertheless the analysis can be extended to other models to study the mismatch in CMOS transistors [1][2][3][4], or to obtain more accurate expressions for 2 T V σ , 2 β σ , considering, for example, the mismatch dependence on the distance between transistors [1,2]. In analog design, it is common to express mismatch in terms of ∆V T , ∆β, the difference between V T , β, of two matched transistors.…”