Understanding Off-Chip Memory Contention of Parallel Programs in Multicore Systems

Abstract

Memory contention is an important performance issue in current multicore architectures. In this paper, we focus on understanding how off-chip memory contention affects the performance of parallel applications. Using measurements conducted on state-of-the-art multicore systems, we observed that off-chip memory traffic is not always bursty, as it was previously reported in literature. Burstiness depends on the problem size. Small problem sizes lead to bursty memory traffic, and generate small off-chip contention. In contrast, when large program sizes cause memory contention, the memory traffic is non-bursty. Based on these observations, we propose an analytical model that relates the growth of memory contention to the number of active cores and to the problem size, for both uniform (UMA) and non-uniform memory access (NUMA) systems. Our model differs from measurements on average by less than 14%. Contention for off-chip memory grows exponentially with the number of active cores, but adding additional memory controllers reduces the memory contention. For programs such as the pentadiagonal solver SP from NPB benchmark, with a large matrix of 162 3 elements (input size C), our analysis shows that memory contention increases the total number of processor cycles to execute the program by more than ten times on a machine with 24 cores.

Towards Modelling Parallelism and Energy Performance of Multicore Systems

“…Using extensive measurement analysis on state of the art multicore systems [8], [9], we conclude that for weak-scaling programs the last-level misses, number of cycles unrelated to memory contention and work cycles do not change significantly when n changes. Furthermore, we study the pattern of burstiness of the memory requests and conclude that large parallel programs do not exhibit bursty memory traffic [9].…”

“…Furthermore, we study the pattern of burstiness of the memory requests and conclude that large parallel programs do not exhibit bursty memory traffic [9]. Based on these insights, we propose a simple single-server queueing model for predicting the number of cycles incurred by a program on a single-socket system.…”

“…The practicality of the models stems from their generality across programming languages/threading packages and architectures, and from new insights on the decrease of memory burstiness in multicore systems, for large problem sizes. These insights are based on extensive experiments on state-of-the-art multicore systems, with core counts up to 4 in ARM systems, and 48 in commodity UMA and NUMA systems [8], [9]. 2) Using predictions of the model, we optimize execution of parallel programs by adjusting the number of cores or the core frequency in systems with dynamic frequency scaling.…”

MAP-numa: Access Patterns Used to Characterize the NUMA Memory Access Optimization Techniques and Algorithms

“…Gaussian computational chemistry code is used in [10]. H.264 video encoding code is used in [17]. Essentially, they are similar to the first category.…”

“…SPLASH2, PARSEC and Advention (a part of the Brazilian Regional Atmosphere Modeling System) were used in [13]. NPB is also used in [12][16] [17]. They measured the runtime before and after the optimization with the well known scientific benchmarks to demonstrate their effectiveness.…”