Understanding sources of ineffciency in general-purpose chips

Abstract

o C To b E r 2 0 1 1 | vo L . 5 4 | N o. 1 0 | c o m m u n i c at i o n s o f t he acm 85 abstractScaling the performance of a power limited processor requires decreasing the energy expended per instruction executed, since energy/op * op/second is power. To better understand what improvement in processor efficiency is possible, and what must be done to capture it, we quantify the sources of the performance and energy overheads of a 720p HD H.264 encoder running on a general-purpose fourprocessor CMP system. The initial overheads are large: the CMP was 500× less energy efficient than an Application Specific Integrated Circuit (ASIC) doing the same job. We explore methods to eliminate these overheads by transforming the CPU into a specialized system for H.264 encoding. Broadly applicable optimizations like single instruction, multiple data (SIMD) units improve CMP performance by 14× and energy by 10×, which is still 50× worse than an ASIC. The problem is that the basic operation costs in H.264 are so small that even with a SIMD unit doing over 10 ops per cycle, 90% of the energy is still overhead. Achieving ASIClike performance and efficiency requires algorithm-specific optimizations. For each subalgorithm of H.264, we create a large, specialized functional/storage unit capable of executing hundreds of operations per instruction. This improves energy efficiency by 160× (instead of 10×), and the final customized CMP reaches the same performance and within 3× of an ASIC solution's energy in comparable area.

Instruction set extensions for Dynamic Time Warping

“…One recent study showed that ISEs could eliminate the energy and performance gaps between software and ASIC implementations of an H.264 encoding, while automating the architectural design and verification process [8]. We believe that our approach achieves principally similar results for matching one 128-element query.…”

“…The SoC will include some amount of specialized hardware for common functions that are performance and/or energy critical, while all other applications run in software. Prior work has shown that application-specific processors with specialized instruction sets (ASIPs) can almost equal the energy efficiency of applicationspecific integrated circuits (ASICs) [8], without sacrificing general-purpose functionality to support other applications.…”

Synthesis of Processor Instruction Sets from High-Level ISA Specifications

“…ASIPs allow adding new functionality to an extensible baseline ISA in the form of Instruction Set Extensions (ISEs), thereby combining flexibility of a general purpose CPU and performance of an ASIC. The key idea is to analyse the application domain and identify repetitive source code fragments that can be replaced by custom ISE instructions to reduce NCL-EEE-MSD-TR-2012-177, Newcastle University 1 A. Mokhov, A. Iliasov, D. Sokolov, M. Rykunov, A. Yakovlev, A. Romanovsky: Synthesis of Processor Instruction Sets from High-level ISA Specifications overheads associated with the instruction fetch cycle and storage of temporary values [22], as well as to enable additional optimisation opportunities in resource allocation, register binding, and port assignment [15] [34].…”

“…Reconfigurable ASIPs address this requirement by combining a static general purpose ISA with a reconfigurable fabric to introduce new functionality when it becomes needed [11] [12]. Reconfigurability and custom instructions also address the issue of energy efficiency (a major concern for the microelectronics industry, particularly in mobile and embedded domains) by power elasticity [38] and by moving computationally intensive algorithms from software to hardware [22][27].…”

Algorithm/Architecture Codesign of Low Power and High Performance Linear Algebra Compute Fabrics

“…It is well known that full-custom, application-specific design of on-chip hardware accelerators, can provide orders of magnitude improvements in both power and performance for a wide variety of application domains [55,154].…”