Understanding yield losses in logic circuits

Appello, D.; Fudoli, A.; Giarda, K.; Tancorre, V.; Gizdarski, Emil; Mathew, B.

doi:10.1109/mdt.2004.21

Cited by 24 publications

(5 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For example, m could be the number of chips on which Scan_Chain_1 passes and N the total number of chips tested for scan chain conti nuity. Both m and N are stored and readily available in the Subdie Instance Summaries table of the Central Data Ware house as described in Section 2. lA, as briefly described above, has been reported in the past [7,9]. It is an extremely powerful, low-cost diagnostic technique that depends only upon the ready availability of ap propriately summarized fail data.…”

Section: Subdie Instance Analysismentioning

confidence: 99%

“…Volume logic diagnosis has been a much researched topic in the test community in the last decade [9,[12][13][14]. Espe cially useful are the techniques that utilize layout information to improve the resolution and accuracy of logic diagnosis [15] and for identifying layout-specific systematic defects [13,16].…”

Section: Volume Diagnosismentioning

confidence: 99%

“…Espe cially useful are the techniques that utilize layout information to improve the resolution and accuracy of logic diagnosis [15] and for identifying layout-specific systematic defects [13,16]. Volume diagnosis has been used to find systematically fail ing standard cells [7,9,14], or specific design features of in terest [13]. More recently, statistical analysis techniques that mine the volume diagnosis results for systematically failing design features have been reported [16].…”

Section: Volume Diagnosismentioning

confidence: 99%

See 2 more Smart Citations

Hard to find, easy to find systematics; just find them

Desineni

Pastel

Kassab

et al. 2010

2010 IEEE International Test Conference

View full text Add to dashboard Cite

In a manufacturing organization, every morning starts with the question: what is the yield today? The cost of wafer manufacturing being fairly constant, product yield is one of the most significant variables for profitability. With the yield paretos increasingly dominated by systematic defects, yield learning based on product test is fast becoming a fundamen tal requirement. For an integrated device manufacturer like IBM, product-based yield learning is even more critical as this drives technology learning as well. In this paper, we will present some of IBM's yield learning techniques and several case studies from high-volume manufacturing. These tech niques extend from test data analysis, to analysis of scan based product diagnosis results, to detailed layout analysis in conjunction with test, diagnosis and inline defect inspection data. We will discuss the increasing levels of complexity asso ciated with the various techniques and argue that an effective yield learning strategy must comprise all of the above.

show abstract

Section: Subdie Instance Analysismentioning

confidence: 99%

Section: Volume Diagnosismentioning

confidence: 99%

Section: Volume Diagnosismentioning

confidence: 99%

See 1 more Smart Citation

Hard to find, easy to find systematics; just find them

Desineni

Pastel

Kassab

et al. 2010

2010 IEEE International Test Conference

View full text Add to dashboard Cite

show abstract

“…While not a common industry practice, the generation of new test responses for increasing diagnosis accuracy has been proposed in [21] and more recently, in [9,15,22].…”

Section: Additional Atpgmentioning

confidence: 99%

Diagnosis of Arbitrary Defects Using Neighborhood Function Extraction

Desineni

Blanton

23rd IEEE VLSI Test Symposium (VTS'05)

View full text Add to dashboard Cite

We present a methodology for diagnosing arbitrary defects in digital integrated circuits (ICs). Rather than using one or a set of fault models in a cause-effect or effect-cause approach, our methodology derives defect behavior from the test set, the circuit and its response, and the physical neighbors that surround a potential defect location. The defect locations themselves are identified using a model-independent stage. The methodology enables accurate identification of defect location and behavior through validation via simulation using passing and additional diagnostic test patterns. A byproduct of our methodology is the distinction that can be made among stuck-fault equivalencies which results in improved diagnostic resolution. Several types of shorts and opens are used to demonstrate the applicability of our approach to the diagnosis of arbitrary defects.

show abstract

“…Failure diagnosis is used to accelerate yield learning in high-volume production. Failure diagnosis is able to distinguish between random production defects and systematic production defects in case a large number of failing devices is analyzed [1,2,3].…”

Section: Introductionmentioning

confidence: 99%