Unified all-digital duty-cycle and phase correction circuit for QDR I/O interface

Ha, Jae-Hwan; Lim, Jeong-Ok; Kim, Y.J.; Jung, Wonjin; Wee, Jae-Kyung

doi:10.1049/el:20080798

Cited by 13 publications

(10 citation statements)

References 6 publications

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“…Therefore, they are not suitable for wide frequency range operation. In [9], the output clock is not phase aligned with the input clock. Compared to prior studies, the proposed ADDCC not only has a wider frequency range, but also has a wider input duty-cycle range.…”

Section: Resultsmentioning

confidence: 99%

“…However, the clock is distributed over the chip using clock buffers, and thus, the duty-cycle of the clock is affected by the unbalanced rise time and fall time of the clock buffers with process, voltage and temperature (PVT) variations. In order to overcome such problem, many approaches have been proposed to adjust the clock duty-cycle to 50% to meet the system requirements, such as pulse-width control loop (PWCL) [1,2] and duty-cycle corrector (DCC) [3,4,5,6,9,10].…”

Section: Introductionmentioning

confidence: 99%

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A wide-range all-digital duty-cycle corrector with output clock phase alignment in 65nm CMOS technology

Chung

Sheng

Shen

2011

IEICE Electron. Express

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Abstract:A wide-range all-digital duty-cycle corrector (ADDCC) with output clock phase alignment is presented in this paper. The proposed ADDCC can correct the duty-cycle error of the input clock to 50% duty-cycle. The acceptable duty-cycle range and frequency range of input clock is from 20% to 80% and from 250 MHz to 1 GHz, respectively. The proposed ADDCC is implemented on a standard performance 65 nm CMOS process, and the power consumption is 1.52 mW at 250 MHz and 5.83 mW at 1 GHz, respectively.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A wide-range all-digital duty-cycle corrector with output clock phase alignment in 65nm CMOS technology

Chung

Sheng

Shen

2011

IEICE Electron. Express

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show abstract

“…Therefore, duty-cycle correction (DCC) circuits [1][2][3][4][5], capable of correcting a clock with an arbitrary duty-cycle to a 50% duty-cycle clock, are widely used in high-speed digital circuits such as microprocessors, memories, and clock recovery applications to improve performance by using both the rising and falling edges of a clock signal. Among non-feedback [1] and feedback DCCs [2][3][4][5], the non-feedback DCCs cannot track PVT variations due to their open-loop characteristic, which causes low performance and limited applications. Feedback DCCs can be classified into three categories: analog [2], digital [3], and mixed-mode [4,5].…”

Section: Introductionmentioning

confidence: 99%

“…Among non-feedback [1] and feedback DCCs [2][3][4][5], the non-feedback DCCs cannot track PVT variations due to their open-loop characteristic, which causes low performance and limited applications. Feedback DCCs can be classified into three categories: analog [2], digital [3], and mixed-mode [4,5]. Analog feedback DCCs usually require a long wake-up time and digital feedback DCCs usually have limited duty-cycle correction range and a relatively large error in duty cycle.…”

Section: Introductionmentioning

confidence: 99%

A 0.5-2.0 GHz Dual-Loop SAR-controlled Duty-Cycle Corrector Using a Mixed Search Algorithm

Han¹,

Kim

2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper presents a fast-lock dual-loop successive approximation register-controlled dutycycle corrector (SARDCC) circuit using a mixed (binary+sequential) search algorithm. A wider dutycycle correction range, higher operating frequency, and higher duty-cycle correction accuracy have been achieved by utilizing the dual-loop architecture and the binary search SAR that achieves the fast dutycycle correcting property. By transforming the binary search SAR into a sequential search counter after the first DCC lock-in, the proposed dual-loop SARDCC keeps the closed-loop characteristic and tracks variations in process, voltage, and temperature (PVT). The measured duty cycle error is less than ±0.86 % for a wide input duty-cycle range of 15-85 % over a wide frequency range of 0.5-2.0 GHz. The proposed dual-loop SARDCC is fabricated in a 0.18-µm, 1.8-V CMOS process and occupies an active area of 0.075 mm 2 .

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“…Therefore, timing and synchronization circuits such as delay-locked loops (DLLs) and phase-locked loops (PLLs) usually consist of a duty-cycle correction (DCC) circuit capable of (527) correcting a clock with an arbitrary duty-cycle to a 50% duty-cycle clock. DCCs can be classified into three categories: analog [1] , digital [2] , and hybrid [3] . Analog DCCs are usually implemented by using a simple negative feedback loop and show better accuracy and a wide duty correction range but are unable to support low-power standby or power-down mode operations.…”

Section: ⅰ Introductionmentioning

confidence: 99%

A CMOS Duty Cycle Corrector Using Dynamic Frequency Scaling for Coarse and Fine Tuning Adjustment

Han¹,

Kim²

2012

Journal of the Institute of Electronics Engineers of Korea

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This paper presents a mixed-mode CMOS duty-cycle corrector (DCC) circuit that has a dynamic frequency scaling (DFS) counter and coarse and fine tuning adjustments. A higher duty-cycle correction accuracy and smaller jitter have been achieved by utilizing the DFS counter that reduces the bit-switching glitch effect of a digital to analog converter (DAC). The proposed circuit has been designed using a 0.18-㎛ CMOS process. The measured duty cycle error is less than ±1.1% for a wide input duty-cycle range of 25-75% over a wide freqeuncy range of 0.5-1.5 GHz.

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Unified all-digital duty-cycle and phase correction circuit for QDR I/O interface

Cited by 13 publications

References 6 publications

A wide-range all-digital duty-cycle corrector with output clock phase alignment in 65nm CMOS technology

A wide-range all-digital duty-cycle corrector with output clock phase alignment in 65nm CMOS technology

A 0.5-2.0 GHz Dual-Loop SAR-controlled Duty-Cycle Corrector Using a Mixed Search Algorithm

A CMOS Duty Cycle Corrector Using Dynamic Frequency Scaling for Coarse and Fine Tuning Adjustment

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