Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs

Abstract

A unified architecture for fast and efficient computation of the set of two-dimensional (2-D) transforms adopted by the most recent state-of-the-art digital video standards is presented in this paper. Contrasting to other designs with similar functionality, the presented architecture is supported on a scalable, modular and completely configurable processing structure. This flexible structure not only allows to easily reconfigure the architecture to support different transform kernels, but it also permits its resizing to efficiently support transforms of different orders (e.g. order-4, order-8, order-16 and order-32). Consequently, not only is it highly suitable to realize high-performance multi-standard transform cores, but it also offers highly efficient implementations of specialized processing structures addressing only a reduced subset of transforms that are used by a specific video standard. The experimental results that were obtained by prototyping several configurations of this processing structure in a Xilinx Virtex-7 FPGA show the superior performance and hardware efficiency levels provided by the proposed unified architecture for the implementation of transform cores for the Advanced Video Coding (AVC), Audio Video coding Standard (AVS), VC-1 and High Efficiency Video Coding (HEVC) standards. In addition, such results also demonstrate the ability of this processing structure to realize multi-standard transform cores supporting all the standards mentioned above and that are capable of processing the 8k Ultra High Definition Television (UHDTV) video format (7,680 × 4,320 at 30 fps) in real time.

FoRTReSS: a flow for design space exploration of partially reconfigurable systems

“…However many works have already been devoted to the implementation of critical processing blocks of H.265/HEVC since the technical content of HEVC was finalized at the beginning of 2013. Table 5 reports the characteristics of three relevant hardware implementations on Virtex FPGAs that can be used to process an early exploration of the acceleration potential with dynamic reconfiguration: a motion estimation engine [11] which is the most computational part of the encoding process, a high performance intra prediction hardware [21] and an accelerator supporting fast forward and inverse two-dimensional transforms [33]. All implementation and performance results come from Xilinx Virtex devices and have been extrapolated to comply with the same video resolution and a running frequency of 100MHz.…”

High‐throughput IDCT architecture for high‐efficiency video coding (HEVC)

“…Rowcolumn decomposition is widely used in the design of the two-dimensional (2-D) transform core, which generally uses two one-dimensional (1-D) cores in conjunction with transposed memory. Nonetheless, numerous architectures for the inverse transform have been developed using this structure to reach a high throughput rate [5][6][7][8][9][10][11]. This approach makes it possible to achieve high throughput; however, it generally involves high area overhead with regard to circuitry.…”

“…Many researchers have sought to implement integer transforms, particularly for HEVC [4][5][6][7][8][9][10][11][12][13]. Rowcolumn decomposition is widely used in the design of the two-dimensional (2-D) transform core, which generally uses two one-dimensional (1-D) cores in conjunction with transposed memory.…”

“…This approach makes it possible to achieve high throughput; however, it generally involves high area overhead with regard to circuitry. Nonetheless, numerous architectures for the inverse transform have been developed using this structure to reach a high throughput rate [5][6][7][8][9][10][11]. To deal with the high-cost overhead, [9] presents a transpose architecture by a cyclic data mapping scheme to reduce Static Random-Access Memory (SRAM) area.…”

An Efficient and Robust High Efficiency Video Coding Framework to Enhance Perceptual Quality of Real-Time Video Frames

“…Blasi et al [11] have presented a technique for minimizing the complexity related to motion compensation. Diaset al [12] have presented an FPGA-based study for performing compression using H.265 protocol using an integrated scheme of the efficient computational process along with 2D transforms. Mu et al [13] have presented a cascaded technique for legacy protocols e.g.…”