Unifying methodologies for high fault coverage concurrent and off-line test of digital filters

Abstract

A low-cost on-line test scheme for digital filters that additionally provides an off-line BIST solution is proposed. The scheme utilizes an invariant of the digital filter in order to detect on-line possible circuit malfunctions. The on-line checking hardware is shared with off-line BIST. The analysis performed indicates that exact 100% fault secureness is attained when the digital filter is designed according to design criteria that we identify in the paper. Furthermore, fault simulations show near 100% fault coverage for off-line BIST.

Concurrent test for digital linear systems

“…The accumulators added for concurrent error checking can be utilized for offline manufacturing testing [2]. The input accumulator can be converted to an arithmetic pattern generator with an additional multiplexer.…”

“…While in the previous implementation such a requirement was not imposed, the bitwidth of the accumulator was larger and the multiplication operation with truncation necessitated a comparable area. The drawback of the second implementation is that the concurrent error-detection hardware cannot be shared with an offline BIST scheme as proposed in [2], which depends on arithmetic pattern generators.…”

Low cost concurrent test implementation for linear digital systems

“…Faults internal to full adder cells, on the other hand, may behave non-monotonically depending on the implementation style. Since adders are linear, the results of [8] guarantee that costeffective ripple-carry adder implementations with monotonic fault behavior indeed exist.…”

“…Monotonic implementation of other adders can be found in [8]. Ripple-carry adders are composed of a chain of full adders.…”