Unique ESD failure mechanism of high voltage LDMOS transistors for very fast transients

Goyal, A.; Whitfield, J.; Hong, Changsoo; Gill, Chai; Zhan, Chenchang; Kushner, V.; Gendron, Amaury; Contractor, S.

doi:10.1109/relphy.2008.4558982

Cited by 4 publications

(1 citation statement)

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“…The unique ESD breakdown mechanism of high voltage LDMOS structures under very fast transients has been reported in Ref. [6]. However, detailed analysis of this phenomena and an improved method are both less documented.…”

Section: Introductionmentioning

confidence: 98%

Analysis of trigger behavior of high voltage LDMOS under TLP and VFTLP stress

et al. 2010

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The physical mechanisms triggering electrostatic discharge (ESD) in high voltage LDMOS power transistors (> 160 V) under transmission line pulsing (TLP) and very fast transmission line pulsing (VFTLP) stress are investigated by TCAD simulations using a set of macroscopic physical models related to previous studies implemented in Sentaurus Device. Under VFTLP stress, it is observed that the triggering voltage of the high voltage LDMOS obviously increases, which is a unique phenomenon compared with the low voltage ESD protection devices like NMOS and SCR. The relationship between the triggering voltage increase and the parasitic capacitances is also analyzed in detail. A compact equivalent circuit schematic is presented according to the investigated phenomena. An improved structure to alleviate this effect is also proposed and confirmed by the experiments.

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Section: Introductionmentioning

confidence: 98%