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A dominant electron trap in boron-doped CZ silicon at Ec −0.41 ± 0.02 eV with a electron capture cross section >10−14 cm2 has been observed with DLTS in 2-step annealed (16 hrs at 800°C + 16 hrs at 1050°C) seed end wafers where oxygen precipitation is pronounced. A strong correlation between the generation lifetime τg (as calculated from junction reverse generation currents) and the density of this trap is also observed. Electron microscopy showed the dominant precipitates to be {100} plate type containing only Si and 0, with dislocations and punched-out loops in close proximity. Wafers from the center- or tang-sections of the ingot or those given a 1-step anneal (conditions which result in much less oxygen precipitation) contain a low density (<1.2 × 1012 cm−3) of a hole trap at Ev +0.25 eV not correlated with Tg. These wafers contain precipitates with a different morphology with much rower or minimal dislocation densities. Possible origins of the lifetime controlling electron trap is discussed.

Abstrqct-A brief review of a recent paper [l] describing a method to electrically determine the effective channel length is presented. The method uses a simplifying approximation. By defining some new terms this application can be avoided leading to a new method. Finally, data is presented comparing the two methods for MOSFET's clearly violating the approximation and exemplifying the general applicability of the new method. I N A RECENT LETTER by Peng and Afromowitz [ l ] a method was proposed to determine the channel length and parasitic drainisource series resistance of a MOSFET. This method uses two devices with different gate lengths, but with other aspects identical. Drain currents as a function of gate bias were analyzed in the linear region of operation. The gate oxide thickness, surface carrier mobilities, effective channel widths, and the threshold voltages were assumed equal. The devices were each biased with the same gate-source voltages and the same drain-source voltages. From these assumptions and test conditions, the following equation was derived:where I d $ and Rt are the source-drain current and resistances, respectively; v d s is the source-drain voltage; and L and DL are the physical gate length and the difference between the physical and effective gate length, respectively.For v d sthe authors derived a simple linear relationship between the source-drain current ratio for the two devices and the difference in their respective currents, given by the following expression:from which the slope A and intercept ( I d s ] / I d~2 ) 0 give AL and R , as follows:R t = s 2 ) 0 1 . (4)Using this approach Peng obtained values for AL and Rt on n-channel MOSFET's.A variation of Peng's method was developed by this author while analyzing MOSFET's with large Rt (i.e., I d S R t was Manuscript (54We obtain the following modification of (1): R d $ = [~L / ( L I -a ) ] ( R d s l -Rr). (6)From ( 6 ) , a simple linear-parametric plot results when 6Rds is plotted as a function of R d s l , A linear extrapolation to the Rdrl axis gives Rt . AL is computed from the slope of (6) and is given by AL=L1-6L/Mwhere M is the slope.To validate this method! devices were tested with Rt = Rdsl or Rds2. Fig. l(a) and (b) present data obtained from devices fabricated in our laboratory. The devices had physical gate lengths of 4.1 and 6.7 pm and were tested with v d s = 0.1 V. Fig. l(a) is the data plotted by Peng's method, the curve would be linear and 8, and AL can be educed, However, this data is clearly nonlinear and the parameters are hopelessly unextractable.In Fig. l(b), the data is plotted by the method given here. The curve is nearly linear for all values of V,,, even for V,, = 20 V, when most of v d s is dropped across R f (taking V R r the least squares fit intersects the Rdsl axis at Rr = 183 C2 and the slope of the line gives AL = 1.62 pm.In summary, we have reviewed Peng's effective gate-length derivation and modified it by avoiding their approximation. This new method was applied to devices fabricated in our laborat...

Epitaxial SiGe/Si layers are being extensively investigated for use in base regions of high-speed heterojunction bipolar-transistors (HBTs). Extended defects can be formed in SiGe/Si layers by ion-implantation. Defects, once formed in the layers, can negatively impact electrical performance and also future reliability of the HBTs. The present study investigates the interaction between selective-implant damage and strained SiGe/Si layers of sub-critical thickness. Implant-damage is observed to form dislocation-sources at the edges of implanted regions in SiGe/Si heterolayers. The dislocation sources produce glide dislocation loops. Segments of these loops glide down to SiGe/Si interfaces causing misfit dislocations to arise at interfaces in the heterolayers. Misfitdislocations are formed in directions parallel to and perpendicular to the <110> edge of the implanted region. Dislocations propagate out to a distance of ∼100-150 nm past the edge of the implant in the case of Si0.9Ge0.1/Si layers of sub-critical thickness. The origin and behavior of these defects is discussed.