Unique Ultra Shallow Junction Scheme with Conventional Activation Process

Tsai, Cheng‐Hung; Lan, Bijian; Lin, Yu-Hua; Chiang, Wen-Tai; Chang, Tzu-Feng; Liu, P.; Pan, Jeng Hung; Liu, Y.; Tsai, Jiunn-Yann; Chen, T.

doi:10.1109/vlsit.2006.1705280

Cited by 1 publication

(1 citation statement)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Table 2 summarizes several reported strain schemes, including uniaxial, biaxial, and hybrid schemes [4,[7][8][10][11][12][13][26][27][28][29][30][31][32]. Some exciting strain schemes may achieve current enhancement near 80%.…”

Section: Benchmarksmentioning

confidence: 99%

Extension of Moore's Law via Strained Technologies- The Strategies and Challenges

Chung

2011

ECS Trans.

View full text Add to dashboard Cite

For recent manufacturable CMOS technologies to extend the Moore's law, the interest in the strain engineering has been speed-up in recent years as a need in further scaling of CMOS devices for high speed and low power applications. Among those reported strain schemes [1-10], process-induced stress technique [1,6,10], strained-SiGe channel devices [3,8], substrate engineering, and hybrid substrate technology [9] have been attractive for high speed and low power logic CMOS technologies. As a consequence, strain-silicon technology has lasted for several generations beyond the 90nm generation node and it now comes to the cross-road of whether we want to use the planar CMOS structure at 20nm-16nm node. Strained technology seems to be one of the efficient approaches whatever the changes of device structure might be. Although some exciting strain schemes may achieve current enhancement that are expected, the reliability issues of strain CMOS devices need to be taken into consideration in the using of strained structures [11][12]. Also, with the further scaling of device dimensions, variability becomes increasingly important. More efforts on the study of strain-induced reliability, variability, device drain current enhancement etc., become more interested and raised more attention.In this talk, the strain-silicon technology since 90nm generation node will be first introduced. Then, the reliability and the design guideline for a trade-off between performance and reliability will be addressed. A technology roadmap in terms of the ballistic transport theory will be demonstrated. Then, the variability of the strained CMOS devices will be tackled, in which a more recently developed discrete dopant profiling [13] in the monitoring of the Ge and Carbon out-diffusion will be demonstrated. Finally, the strategies of strained-silicon device design with the trade-off between reliability, variability, and performance will be introduced. References

show abstract

Section: Benchmarksmentioning

confidence: 99%

Extension of Moore's Law via Strained Technologies- The Strategies and Challenges

Chung

2011

ECS Trans.

View full text Add to dashboard Cite

show abstract

Unique Ultra Shallow Junction Scheme with Conventional Activation Process

Cited by 1 publication

References 2 publications

Extension of Moore's Law via Strained Technologies- The Strategies and Challenges

Extension of Moore's Law via Strained Technologies- The Strategies and Challenges

Contact Info

Product

Resources

About