For the first time, 15% and 7% drive current improvement is simultaneously achieved in both N/PMOS by adopting ultimate spacer process (USP) with a single stress liner. High out-of-plane stress in the channel accounts for the simultaneously enhanced drive current in N/PMOS. A 15% speed enhancement without compromising yield and product qualification in Field-Programmable Gate Arrays (FPGA) confirms immediate manufacturing feasibility of USP. This process provides a unique approach to significantly enhance device performance for 65nm CMOS technology and beyond. Extreme current increase of 25% in NMOS and 35% in PMOS can be achieved by applying additional strain enhancement methods.

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SummaryA novel unified black‐box macro model for analog circuits is presented. This black‐box macro model enables the creation of a high‐accuracy DC and AC macro model by modeling the port voltages and currents of analog circuits using an artificial neural network (ANN). The modeling process for different analog circuit blocks is the same, as the model can be modeled by extracting only the port values. The operational amplifier (OPAMP), which is an important module of the analog circuit, is taken as an example for the verification of the model proposed in this work. The black‐box macro model of OPAMP is used for DC, AC, and transient simulations. The simulation speed of the black‐box macro model is much better than that of the transistor‐level model, and the trade‐off between accuracy and speed can be freely adjusted. The black‐box macro model of OPAMP is also validated by bandgap and low dropout regulators (LDO). To verify the accuracy of the model, the experimental measurement results of the LDO circuit fabricated in the 0.18 μm process have been obtained. Compared with the measurement results, the simulation results of both transistor and black‐box macro models have high accuracy. Those results demonstrate the great potential of the black‐box macro model in analog circuit design and simulation.

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