For the first time, 15% and 7% drive current improvement is simultaneously achieved in both N/PMOS by adopting ultimate spacer process (USP) with a single stress liner. High out-of-plane stress in the channel accounts for the simultaneously enhanced drive current in N/PMOS. A 15% speed enhancement without compromising yield and product qualification in Field-Programmable Gate Arrays (FPGA) confirms immediate manufacturing feasibility of USP. This process provides a unique approach to significantly enhance device performance for 65nm CMOS technology and beyond. Extreme current increase of 25% in NMOS and 35% in PMOS can be achieved by applying additional strain enhancement methods.

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