Universal masking on logic gate level

Golić, Jovan Dj.; Menicocci, Renato

doi:10.1049/el:20040385

Cited by 32 publications

(15 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…If the DTS is large enough, it offers a possibility to DPA attacks to find the key. The use of MUX to realize masked circuits for AND (OR) gates in [4] also incur the same problem.…”

Section: Dissipation Timing Skews (Dts)mentioning

confidence: 99%

See 1 more Smart Citation

Overcoming Glitches and Dissipation Timing Skews in Design of DPA-Resistant Cryptographic Hardware

Lin

Fang

Yang

et al. 2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

View full text Add to dashboard Cite

show abstract

“…If the DTS is large enough, it offers a possibility to DPA attacks to find the key. The use of MUX to realize masked circuits for AND (OR) gates in [4] also incur the same problem.…”

Section: Dissipation Timing Skews (Dts)mentioning

confidence: 99%

“…A complete design of AES algorithm with masking at gate-level was presented in [15]. Universal masking for random logic was developed in [4]. However, these masking approaches were shown to be unable to resist DPA attacks in the presence of glitches [8,13].…”

Section: Introductionmentioning

confidence: 99%

Overcoming Glitches and Dissipation Timing Skews in Design of DPA-Resistant Cryptographic Hardware

Lin

Fang

Yang

et al. 2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

View full text Add to dashboard Cite

show abstract

“…There are various countermeasures that have been proposed in the literature [2]- [10] to protect cryptographic implementations and are employed at the algorithmic level, architecture level, and cell (gate) level. Hiding [2] and masking [3] are amongst the most common countermeasures at cell level.…”

Section: Introductionmentioning

confidence: 99%

A novel power analysis attack resilient adiabatic logic without charge sharing

Raghav

Bartlett

Kale

2017

2017 European Conference on Circuit Theory and Design (ECCTD)

View full text Add to dashboard Cite

Abstract-In this paper, we propose a novel power analysis attack resilient adiabatic logic which, unlike existing secure adiabatic logic designs doesn't require any charge sharing between the output nodes of the gates. The proposed logic also removes the non-adiabatic losses (NAL) during the evaluation phase of the power-clock. We investigate and compare our proposed and the existing secure adiabatic logic across a range of "power-clock" frequencies on the basis of percentage Normalized Energy Deviation (%NED), percentage Normalized Standard Deviation(%NSD) and average energy dissipation. The prelayout and post-layout simulation results show that our proposed logic exhibits the least value of %NED and %NSD in comparison to the existing secure adiabatic logic designs at the frequency ranging from 1MHz to 100MHz. Also, our proposed logic consumes the lowest energy.

show abstract

“…The effort to achieve invulnerability against DPA attacks is shifted from the transistor level towards the cell level. This approach involves cell-level masking schemes presented in [30] and [10], as well as dual-rail logic styles like WDDL [29] or MDPL [23]. The security analysis of the masking approaches in [18] and [26] revealed that the occurrence of glitches significantly reduces the resistance against PA attacks.…”

Section: Introductionmentioning

confidence: 99%

Masked Dual-Rail Precharge Logic Encounters State-of-the-Art Power Analysis Methods

Moradi

Kirschbaum

Eisenbarth

et al. 2012

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

Abstract-Latest evaluation of the state-of-the-art iMDPL logic style has shown small information leakage compared to its predecessor version MDPL. Concurrently, new advanced power analysis attacks specifically targeting iMDPL have been proposed. Up to now, these attacks are purely theoretic and have not been applied to an implementation. We present a comprehensive analysis of iMDPL, backed by real measurements collected from a 180 nm iMDPL prototype chip. We thoroughly study the extent of remaining information leakage of iMDPL by applying all relevant attacks. Our investigation shows the vulnerability of the target device, a standalone AES core, to several of the advanced attack methods. In comparison to conventional power analysis attacks, the advanced attacks need less power measurements to obtain meaningful results. With the help of logic level simulations routing imbalances between complementary mask trees are identified as a major source of leakage.

show abstract

Universal masking on logic gate level

Cited by 32 publications

References 2 publications

Overcoming Glitches and Dissipation Timing Skews in Design of DPA-Resistant Cryptographic Hardware

Overcoming Glitches and Dissipation Timing Skews in Design of DPA-Resistant Cryptographic Hardware

A novel power analysis attack resilient adiabatic logic without charge sharing

Masked Dual-Rail Precharge Logic Encounters State-of-the-Art Power Analysis Methods

Contact Info

Product

Resources

About