Universal number posit arithmetic generator on FPGA

Jaiswal, Manish Kumar; So, Hayden Kwok-Hay

doi:10.23919/date.2018.8342187

Cited by 43 publications

(25 citation statements)

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“…Another Posit arithmetic core (called PAU, Posit Arithmetic Unit) generator is presented in [46] where generators for Posit adder and multiplier are proposed. The design results show a reduction in area occupation referring to [44] both for adder and multiplier, as well as a reduction in power consumption for 8-bit Posits. For 16-bit Posits the results are overturned in favour of the other implementation, as well as for 32-bit Posits.…”

Section: B Hardware Implementations Of the Posit Processing Unitmentioning

confidence: 96%

“…Some work has already been done to implement Posit units on FPGAs, in order to provide efficient and optimized hardware implementation of Posit arithmetic. In [44] an algorithmic flow and architecture generator for Posit numbers In [45] a Posit core generator called POSGEN is proposed. In addition, the FPGA design has been enriched with an extension of the BLAS library for the Posit numbers called PBLAS, in order to connect the FPGA through the Intel OpenCL libraries.…”

Section: B Hardware Implementations Of the Posit Processing Unitmentioning

confidence: 99%

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Novel Arithmetics in Deep Neural Networks Signal Processing for Autonomous Driving: Challenges and Opportunities

Cococcioni

Rossi

Ruffaldi

et al. 2021

IEEE Signal Process. Mag.

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This paper focuses on trends, opportunities and challenges of novel arithmetics for DNN signal processing, with particular reference to assisted and autonomous driving applications. Due to strict constrains in terms of latency, dependability and security of autonomous driving, machine perception (i.e. detection or decisions tasks) based on DNN can not be implemented relying on a remote cloud access. These tasks must be performed in real-time on embedded systems on-board the vehicle, particularly for the inference phase (considering the use of DNNs pre-trained during an off-line step). When developing a DNN computing platform, the choice of the computing arithmetics matters. Moreover, functional safe applications like autonomous driving pose severe constraints on the effect that signal processing accuracy has on final rate of wrong detection/decisions. Hence, after reviewing the different choices and trade-off concerning arithmetics, both in academia and industry, we highlight the issues in implementing DNN accelerators to achieve accurate and low-complex processing of automotive sensor signals (the latter coming from diverse sources like cameras, radars, lidars, ultrasonics). The focus is on both on general-purpose operations massively used in DNN like multiply, accumulation, compare, or on specific functions like for example sigmoid or hyperbolic tangent, used for neuron activation.

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Section: B Hardware Implementations Of the Posit Processing Unitmentioning

confidence: 96%

Section: B Hardware Implementations Of the Posit Processing Unitmentioning

confidence: 99%

Novel Arithmetics in Deep Neural Networks Signal Processing for Autonomous Driving: Challenges and Opportunities

Cococcioni

Rossi

Ruffaldi

et al. 2021

IEEE Signal Process. Mag.

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“…This format has been proven to match single precision accuracy performance with only 16 bits used for the representation [9,12,16,17,24]. Furthermore, the first hardware implementations of this novel type are very promising in terms of energy consumption and area occupation [10,20,28].…”

Section: Introductionmentioning

confidence: 99%

Vectorizing posit operations on RISC-V for faster deep neural networks: experiments and comparison with ARM SVE

Cococcioni

Rossi

Ruffaldi³

et al. 2021

Neural Comput & Applic

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With the arrival of the open-source RISC-V processor architecture, there is the chance to rethink Deep Neural Networks (DNNs) and information representation and processing. In this work, we will exploit the following ideas: i) reduce the number of bits needed to represent the weights of the DNNs using our recent findings and implementation of the posit number system, ii) exploit RISC-V vectorization as much as possible to speed up the format encoding/decoding, the evaluation of activations functions (using only arithmetic and logic operations, exploiting approximated formulas) and the computation of core DNNs matrix-vector operations. The comparison with the well-established architecture ARM Scalable Vector Extension is natural and challenging due to its closedness and mature nature. The results show how it is possible to vectorize posit operations on RISC-V, gaining a substantial speed-up on all the operations involved. Furthermore, the experimental outcomes highlight how the new architecture can catch up, in terms of performance, with the more mature ARM architecture. Towards this end, the present study is important because it anticipates the results that we expect to achieve when we will have an open RISC-V hardware co-processor capable to operate natively with posits.

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Section: Introductionmentioning

confidence: 99%

“…Earlier related hardware solutions on posit includes [10]- [13]. The initial work on posit hardware research [10], [13] are proposed by the authors which briefly includes the primary on posit arithmetic generators. Following these initial work, [11] has proposed a fixed width (32-bit) posit adder and multiplier architectures, and [12] has briefly presented a (proprietary) generator for posit adder and multiplier.…”

Section: Introductionmentioning

confidence: 99%

PACoGen: A Hardware Posit Arithmetic Core Generator

Jaiswal

2019

IEEE Access

Self Cite

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This paper proposes open-source hardware Posit Arithmetic Core Generator (PACoGen) for the recently developed universal number posit number system, along with a set of pipelined architectures. The posit number system composed of a run-time varying exponent component, which is defined by a composition of varying length ''regime-bit'' and ''exponent-bit'' (with a maximum size of ES bits, the exponent size). This in effect also makes the fraction part to vary at run-time in size and position. These run-time variations inherit an interesting hardware design challenge for posit arithmetic architectures. The posit number system, being at an infant stage of its development, possess very limited hardware solutions for its arithmetic architectures. In this view, this paper targets the algorithmic development and generic HDL generators (PACoGen) for basic posit arithmetic. The proposed open source PACoGen currently includes the adder/subtractor, multiplier, and division arithmetic. The PACoGen can provide the Verilog HDL code respective posit arithmetic for any given posit word width (N) and exponent size (ES), as defined under the posit number system. Further, pipelined architectures of 32-bit posit with 6-bit exponent size are also proposed and discussed for addition/subtraction, multiplication, and division arithmetic. The proposed posit arithmetic architectures are demonstrated on the Virtex-7 (xc7vx330t-3ffg1157) FPGA device as well as Nangate 15 nm ASIC platform.The PACoGen would open a gateway for further posit arithmetic hardware exploration and evaluation.

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Universal number posit arithmetic generator on FPGA

Cited by 43 publications

References 1 publication

Novel Arithmetics in Deep Neural Networks Signal Processing for Autonomous Driving: Challenges and Opportunities

Novel Arithmetics in Deep Neural Networks Signal Processing for Autonomous Driving: Challenges and Opportunities

Vectorizing posit operations on RISC-V for faster deep neural networks: experiments and comparison with ARM SVE

PACoGen: A Hardware Posit Arithmetic Core Generator

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