Unsupervised heart-rate estimation in wearables with Liquid states and a probabilistic readout

Das, Anup; Pradhapan, Paruthi; Groenendaal, Willemijn; Adiraju, Prathyusha; Rajan, Raj Thilak; Catthoor, Francky; Schaafsma, Siebren; Krichmar, Jeffrey L.; Dutt, Nikil; Hoof, Chris Van

doi:10.1016/j.neunet.2017.12.015

Cited by 89 publications

(59 citation statements)

References 86 publications

(141 reference statements)

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“…In [4], LSM was used for movement prediction task and was shown to perform a non-linear technique of Kernal Principal Component Analysis. Speech recognition, time series prediction, and robot control are few of the many versatile applications for which LSM has demonstrated excellent performance [2], [5]- [7]. (a) Conceptual description: Spikes generated in the cochlea (ear) travel to the auditory cortex where a randomly connected recurrent neural network acts as a reservoir of a liquid where input spikes produce a "ripple-like" memory in the network.…”

Section: Introductionmentioning

confidence: 99%

Predicting Performance using Approximate State Space Model for Liquid State Machines

Gorad

Saraswat

Ganguly

2019

2019 International Joint Conference on Neural Networks (IJCNN)

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Liquid State Machine (LSM) is a brain-inspired architecture used for solving problems like speech recognition and time series prediction. LSM comprises of a randomly connected recurrent network of spiking neurons. This network propagates the non-linear neuronal and synaptic dynamics. Maass et al. have argued that the non-linear dynamics of LSMs is essential for its performance as a universal computer. Lyapunov exponent (µ), used to characterize the non-linearity of the network, correlates well with LSM performance. We propose a complementary approach of approximating the LSM dynamics with a linear state space representation. The spike rates from this model are well correlated to the spike rates from LSM. Such equivalence allows the extraction of a memory metric (τM ) from the state transition matrix. τM displays high correlation with performance. Further, high τM system require lesser epochs to achieve a given accuracy. Being computationally cheap (1800× time efficient compared to LSM), the τM metric enables exploration of the vast parameter design space. We observe that the performance correlation of the τM surpasses the Lyapunov exponent (µ), (2 − 4× improvement) in the high-performance regime over multiple datasets. In fact, while µ increases monotonically with network activity, the performance reaches a maxima at a specific activity described in literature as the edge of chaos. On the other hand, τM remains correlated with LSM performance even as µ increases monotonically. Hence, τM captures the useful memory of network activity that enables LSM performance. It also enables rapid design space exploration and fine-tuning of LSM parameters for high performance.

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Section: Introductionmentioning

confidence: 99%

Predicting Performance using Approximate State Space Model for Liquid State Machines

Gorad

Saraswat

Ganguly

2019

2019 International Joint Conference on Neural Networks (IJCNN)

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“…Examples of theoretical neural processing frameworks that require variability can be found in the domain of ensemble learning 53 , reservoir computing 54 and liquid state machines 55 . Current efforts in neuromorphic engineering for implementing such frameworks to solve spatio-temporal pattern recognition problems rely on the variability provided by transistor device-mismatch effects [56][57][58][59][60] . Integration of memristive devices with inhomogeneous properties in such architectures can provide a richer set of distributions useful for enhancing the computational abilities of these networks.…”

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confidence: 99%

A recipe for creating ideal hybrid memristive-CMOS neuromorphic processing systems

Chicca

Indiveri

2020

Applied Physics Letters

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The development of memristive device technologies has reached a level of maturity to enable the design of complex and large-scale hybrid memristive-CMOS neural processing systems. These systems offer promising solutions for implementing novel in-memory computing architectures for machine learning and data analysis problems. We argue that they are also ideal building blocks for the integration in neuromorphic electronic circuits suitable for ultra-low power brain-inspired sensory processing systems, therefore leading to the innovative solutions for always-on edge-computing and Internet-of-Things (IoT) applications. Here we present a recipe for creating such systems based on design strategies and computing principles inspired by those used in mammalian brains. We enumerate the specifications and properties of memristive devices required to support always-on learning in neuromorphic computing system and to minimize their power consumption. Finally, we discuss in what cases such neuromorphic systems can complement conventional processing ones and highlight the importance of exploiting the physics of both the memristive devices and of the CMOS circuits interfaced to them.Neuromorphic computing has recently received considerable attention as a discipline that can offer promising technological solutions for implementing power-and size-efficient sensory-processing, learning, and Artificial Intelligence (AI) applications 1-5 , especially in cases in which the computing system has to operate autonomously "at the edge", i.e., without having to connect to powerful (but power hungry) server farms in the "cloud". The term "neuromorphic" was originally coined in the early 90's by Carver Mead to refer to mixed signal analog/digital Very Large Scale Integration (VLSI) computing systems based on the organizing principles used by the biological nervous systems 6 . In that context, "neuromorphic engineering" emerged as an interdisciplinary research field deeply rooted in biology that focused on building electronic neural processing systems by exploiting the physics of silicon to directly "emulate" the bio-physics of real neurons and synapses. More recently the definition of the term "neuromorphic" has been extended in two additional directions: on one hand to describe more generic spike-based processing systems engineered to "simulate" spiking neural networks for the exploration of large-scale computational neuroscience models 7-9 ; and on the other hand to describe dedicated electronic neural architectures that make use of both electronic Complementary Metal-Oxide Semiconductor (CMOS) circuits and memristive devices to implement neuron and synapse circuits 10,11 .Another recent and very promising trend in developing dedicated hardware architectures for building accelerated simulators of artificial neural networks is related to the field of machine learning and AI 12,13 . The types of neural networks being proposed within this context are only loosely inspired by biology, are aimed at high accuracy pattern recognition based on large...

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“…Das et al [18] heartbeat estimation (HE) Unsupervised, LSM (64, 16) is input to Noxim++, which can incorporate details of a real chip (CxQuad in Figure 4). It is also possible to replace Noxim++ with actual CxQuad or other neuromorphic chip directly, making the framework similar to PACMAN.…”

Section: Approach Application Topologymentioning

confidence: 99%

Mapping of local and global synapses on spiking neuromorphic hardware

Das

Huynh

et al. 2018

2018 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Spiking Neural Networks (SNNs) are widely deployed to solve complex pattern recognition, function approximation and image classification tasks. With the growing size and complexity of these networks, hardware implementation becomes challenging because scaling up the size of a single array (crossbar) of fully connected neurons is no longer feasible due to strict energy budget. Modern neromorphic hardware integrates small-sized crossbars with time-multiplexed interconnects. Partitioning SNNs becomes essential in order to map them on neuromorphic hardware with the major aim to reduce the global communication latency and energy overhead. To achieve this goal, we propose our instantiation of particle swarm optimization, which partitions SNNs into local synapses (mapped on crossbars) and global synapses (mapped on time-multiplexed interconnects), with the objective of reducing spike communication on the interconnect. This improves latency, power consumption as well as application performance by reducing inter-spike interval distortion and spike disorders. Our framework is implemented in Python, interfacing CARLsim, a GPU-accelerated application-level spiking neural network simulator with an extended version of Noxim, for simulating time-multiplexed interconnects. Experiments are conducted with realistic and synthetic SNN-based applications with different computation models, topologies and spike coding schemes. Using power numbers from in-house neuromorphic chips, we demonstrate significant reductions in energy consumption and spike latency over PACMAN, the widely-used partitioning technique for SNNs on SpiNNaker.

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Unsupervised heart-rate estimation in wearables with Liquid states and a probabilistic readout

Cited by 89 publications

References 86 publications

Predicting Performance using Approximate State Space Model for Liquid State Machines

Predicting Performance using Approximate State Space Model for Liquid State Machines

A recipe for creating ideal hybrid memristive-CMOS neuromorphic processing systems

Mapping of local and global synapses on spiking neuromorphic hardware

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