Uprooting defects to enable high-performance III–V optoelectronic devices on silicon

Abstract

The monolithic integration of III-V compound semiconductor devices with silicon presents physical and technological challenges, linked to the creation of defects during the deposition process. Herein, a new defect elimination strategy in highly mismatched heteroepitaxy is demonstrated to achieve a ultra-low dislocation density, epi-ready Ge/Si virtual substrate on a wafer scale, using a highly scalable process. Dislocations are eliminated from the epilayer through dislocation-selective electrochemical deep etching followed by thermal annealing, which creates nanovoids that attract dislocations, facilitating their subsequent annihilation. The averaged dislocation density is reduced by over three orders of magnitude, from ~108 cm−2 to a lower-limit of ~104 cm−2 for 1.5 µm thick Ge layer. The optical properties indicate a strong enhancement of luminescence efficiency in GaAs grown on this virtual substrate. Collectively, this work demonstrates the promise for transfer of this technology to industrial-scale production of integrated photonic and optoelectronic devices on Si platforms in a cost-effective way.

Lattice Strain and Defects Analysis in Nanostructured Semiconductor Materials and Devices by High‐Resolution X‐Ray Diffraction: Theoretical and Practical Aspects

“…[177] However, such approaches have been adopted only in a limited way due to the generation of a high density of defects in the epitaxial heterostructure on silicon due to the large lattice and thermal expansion coefficient mismatch between the two materials. [178] For the reduction of lattice defects, several epitaxial growth methods have been developed: the epitaxial lateral growth, the domain-matched epitaxy [179] and the integration of buffer layers such as low-temperature buffer layers, lattice-engineered buffer layers and metamorphic buffer layers. These methods allow combining a wide variety of different semiconductors to be grown on lattice-mismatched substrates by controlling the density of defects such as stacking faults, misfit, and threading dislocations.…”

Catalysis-Free Growth of III-V Core-Shell Nanowires on p-Si for Efficient Heterojunction Solar Cells with Optimized Window Layer

“…However, the high cost associated with their raw materials such as gallium and arsenide and wafer manufacturing are a setback for expanding the compound semiconductors industry. Therefore, instead of using thick and single-crystalline wafers, the hetero-epitaxial growth of III-V compound semiconductors on Si has been highlighted for decades [8][9][10][11][12][13].…”

Thinned GaInP/GaInAs/Ge solar cells grown with reduced cracking on Ge|Si virtual substrates

“…With this method, they attained GaInP/GaInAs/Ge|Si triple-junction solar cell (3JSC) exhibiting an external quantum efficiency (EQE) comparable to the samples grown on standard Ge substrates, but with a significant voltage loss attributed to an imperfect growth on the coalesced Ge template. Bioud Final version of this paper published in Solar Energy Materials and Solar Cells DOI: https://doi.org/10.1016/j.solmat.2021.111034 2 et al used embedded nanovoids at the Ge|Si interface by electrochemical porosification plus annealing, to achieve lower TDD, but which could be used also for reduced cracking [17]. Another approach by Oh et al consisted on inducing the geometrically controlled formation of cracks by a notch pattern applied to the Si substrate, strategically arranged to enable the fabrication of the solar cell devices in the resulting crack-free regions [18].…”