Use of arbiter physical unclonable function to solve identification problem of digital devices

Klybik, Vladimir P.; Ivaniuk, Alexander A.

doi:10.3103/s0146411615030049

Cited by 11 publications

(7 citation statements)

References 6 publications

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“…From the experimental analysis found the uniqueness (~47%), randomness (79%) and steadiness (82%).to enhance the reliability P. Klybik and A. A. Ivaniuk [27] designed a 128-stage arbiter PUF architecture in Spartan 3E -XC3s500e and estimated the reliability (91%) and uniqueness (48%).…”

Section: Delay Based Arbiter Based Pufsmentioning

confidence: 99%

A secure arbiter physical unclonable functions (PUFs) for device authentication and identification

Kurra¹,

Nelakuditi²

2019

IJEEI

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Recent fourth industrial revolution, industry4.0 results in lot of automation of industrial processes and brings intelligence in many home appliances in the form of IoT, enhances M2M / D2D communication where electronic devices play a prominent role. It is very much necessary to ensure security of those devices. To provide reliable authentication and identification of each device and to abort the counterfeiting from the unauthorized foundries Physical Unclonable Functions (PUFs) emerged as a one of the promising cryptographic hardware security solution. PUF is function, mathematically modeled by using uncontrollable/ unavoidable random variances of the fabrication process of the ICs. These variances can generate unpredictable, random responses can be used to overcome the difficulties such as storing the keys in non-volatile memories (NVMs) in the classical cryptography. A wide variety of PUF architectures such as Arbiter PUFs, Ring oscillator PUFs, SRAM PUFs proposed by authors. But due to its design complexity and low cost, Delay based Arbiter PUFs (D-PUFs) are considering to be a one of the security primitives in authentication applications such as low-cost IoT devices for secure key generation. This paper presents a review on the different types of Delay based PUF architectures proposed by the various authors, sources to exhibit the physical disorders in ICs, methods to estimate the Performance metrics and applications of PUF in different domains.

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Section: Delay Based Arbiter Based Pufsmentioning

confidence: 99%

A secure arbiter physical unclonable functions (PUFs) for device authentication and identification

Kurra¹,

Nelakuditi²

2019

IJEEI

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“…However, this technique can result in unbalanced responses and increased overhead of detecting and recoding meta-stabilization states. More arbiters can also be added to reduce the number of utilizable challenges and improve the reliability of the response at the expense of the hardware overhead [18]. In addition, the outputs of multiple arbiters are correlated, which can compromise the unpredictability of the response.…”

Section: Introductionmentioning

confidence: 99%

A Highly Reliable Arbiter PUF With Improved Uniqueness in FPGA Implementation Using Bit-Self-Test

Chen

Zhang

et al. 2020

IEEE Access

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Physically unclonable functions (PUFs) promise to be a critical hardware primitive for billions of Internet of Things (IoT) devices. The arbiter PUF (A-PUF) is one of the most well-known PUF circuits. However, its FPGA implementation has a poor reliability, and error correction codes (ECCs) are usually needed to eliminate the noise in the responses, which incur additional high hardware overhead and require NVM for helper data storage. In this paper, we present a highly reliable arbiter PUF with improved uniqueness using the bit-self-test (BST) strategy. A delay detection circuit is added into a classical arbiter PUF to test the delay deviation that produces each bit of the PUF response in real-time and mark the response as reliable using a reliability flag when the delay deviation is significantly more than a predefined threshold. Then, the robust responses can be used. We implemented the BST-arbiter PUF on a Xilinx Artix 7 FPGA. The test results show that the selected responses achieve outstanding performance where the bit error rate is less than 10-9 , the bias is 50.3%, and the uniqueness is 49.1%. Thus, the BST-APUF, which drastically reduced the ECC overhead, can be applied to lightweight cryptography applications.

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“…However, this technique may lead to unbalanced response digits as well as detection and recoding overheads of metastable states. More arbiters can also be added to decrease the number of utilizable challenges and increase the reliability of the response at the expenses of hardware overhead [24]. Besides, the outputs of multiple arbiters are correlated, which may compromise the response unpredictability.…”

Section: Introductionmentioning

confidence: 99%

Reliable and Modeling Attack Resistant Authentication of Arbiter PUF in FPGA Implementation With Trinary Quadruple Response

Zalivaka

Ivaniuk

Chang

2019

IEEE Trans.Inform.Forensic Secur.

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Field programmable gate array (FPGA) is a potential hotbed for malicious and counterfeit hardware infiltration. Arbiter based physical unclonable function (A-PUF) has been widely regarded as a suitable lightweight security primitive for FPGA bitstream encryption and device authentication. Unfortunately, metastability of flip-flop gives rise to poor A-PUF reliability in FPGA implementation. Its linear additive path delays are also vulnerable to modeling attacks. Most reliability enhancement techniques tend to increase the response predictability and ease machine learning attacks. This paper presents a robust device authentication method based on the FPGA implementation of a reliability enhanced A-PUF with trinary digit (trit) quadruple responses. A two flip-flop arbiter is used to produce a trit for metastability detection. By considering the ordered responses to all four combinations of first and last challenge bits, each quadruple response can be compressed into a quadbit that represents one of the five classes of trit quadruple response with greater reproducibility. This challenge-response quadruple classification not only greatly reduces the burden of error correction at the device but also enables a precise A-PUF model to be built at the server without having to store the complete challenge-response pair (CRP) set for authentication. Besides, the real challenge to the A-PUF is generated internally by a lossy, nonlinear and irreversible maximum length signature generator at both the server and device sides to prevent the naked CRP from being machine learned by the attacker. The A-PUF with short repetition code of length five has been tested to achieve a reliability of 1.0 over the full operating temperature range of the target FPGA board with lower hardware resource utilization than other modeling attack resilient strong PUFs. The proposed authentication protocol has also been experimentally evaluated to be practically secure against various machine learning attacks including evolutionary strategy covariance matrix adaptation.

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Use of arbiter physical unclonable function to solve identification problem of digital devices

Abstract: An arbiter physical unclonable function (A PUF) for solving the identification problem of digital devices is investigated. Conducted experiments by the example of a Xilinx SPARTAN 3E XC3s500e 5FG320 logic integrated circuit on a field programmable gate array (FPGA) are described.

Cited by 11 publications

References 6 publications

A secure arbiter physical unclonable functions (PUFs) for device authentication and identification

A secure arbiter physical unclonable functions (PUFs) for device authentication and identification

A Highly Reliable Arbiter PUF With Improved Uniqueness in FPGA Implementation Using Bit-Self-Test

Reliable and Modeling Attack Resistant Authentication of Arbiter PUF in FPGA Implementation With Trinary Quadruple Response

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