Use of multicore processors in avionics systems and its potential impact on implementation and certification

Kinnan, L.

doi:10.1109/dasc.2009.5347560

Cited by 32 publications

(20 citation statements)

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“…cache sharing [26,48], cache coherence [26], and the cache replacement policy [2]. Cache sharing is present on platforms where the cores share one or more levels of cache.…”

Section: Cachesmentioning

confidence: 99%

“…Another problem is that the cores may try to access the cache at the same time and one core will block the other core's access, which will introduce delays for the blocked core and timing-variability in the system. To achieve the required performance in IMA systems, using the L2 cache is important in time and space partitioned RTOSes [48] and the inter-core interference problem needs to be addressed.…”

Section: Cachesmentioning

confidence: 99%

“…The internal workings of the interconnect and how it prioritizes the requests are often part of the manufacturer's intellectual property. In a safety-critical system the configuration of the interconnect cannot be ignored since it can cause a core to be blocked by another core accessing a resource in parallel [48].…”

Section: Interconnectmentioning

confidence: 99%

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Timing Predictability in Future Multi-Core Avionics Systems

Löfwenmark¹

2017

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With more functionality added to safety-critical avionics systems, new platforms are required to offer the computational capacity needed. Multi-core platforms offer a potential that is now being explored, but they pose significant challenges with respect to predictability due to shared resources (such as memory) being accessed from several cores in parallel. Multi-core processors also suffer from higher sensitivity to permanent and transient faults due to shrinking transistor sizes.This thesis addresses several of these challenges. First, we review major contributions that assess the impact of fault tolerance on worst-case execution time of processes running on a multi-core platform. In particular, works that evaluate the timing effects using fault injection methods. We conclude that there are few works that address the intricate timing effects that appear when inter-core interferences due to simultaneous accesses of shared resources are combined with the fault tolerance techniques. We assess the applicability of the methods to COTS multi-core processors used in avionics. We identify dark spots on the research map of the joint problem of hardware reliability and timing predictability for multi-core avionics systems.Next, we argue that the memory requests issued by the real-time operating systems (RTOS) must be considered in resource-monitoring systems to ensure proper execution on all cores.We also adapt and extend an existing method for worst-case response time analysis to fulfill the specific requirements of avionics systems. We relax the requirement of private memory banks to also allow cores to share memory banks.

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“…cache sharing [26,48], cache coherence [26], and the cache replacement policy [2]. Cache sharing is present on platforms where the cores share one or more levels of cache.…”

Section: Cachesmentioning

confidence: 99%

Section: Cachesmentioning

confidence: 99%

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Timing Predictability in Future Multi-Core Avionics Systems

Löfwenmark¹

2017

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“…Using multicore processors in safety-critical systems raises some issues that have to be solved (Kinnan, 2009). The most important ones are related to spatial and temporal isolation at the hardware level.…”

Section: Multicore Platformsmentioning

confidence: 99%

Safety Concept for a Mixed Criticality On-Board Software System ∗

et al. 2015

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This paper presents a safety concept for the on-board software system of the UPMSat-2 experimental satellite. Subsystems with different criticality levels are assigned to different partitions in a partitioned software architecture. The architecture is based on XtratuM, an open-source virtualization kernel, and ORK+, an open-source real-time kernel for highintegrity systems. The safety requirements of the system are analysed, and a safety concept is developed based on the partitioned software architecture. The properties of the implementation resulting from the approach are discussed, and guidelines for future developments are proposed.

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“…Increasing numbers of cores in modern processors enable the integration of new software features in safety-critical systems (SCSs). Initially, such new architectures posed some problems to developers of SCSs [19]. In the meantime, efforts have been made to overcome these problems by appropriate hardware and software design (see e.g.…”

Section: Introductionmentioning

confidence: 99%

Support for the logical execution time model on a time-predictable multicore processor

2016

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The logical execution time (LET) model increases the compositionality of real-time task sets. Removal or addition of tasks does not influence the communication behavior of other tasks. In this work, we extend a multicore operating system running on a timepredictable multicore processor to support the LET model. For communication between tasks we use message passing on a timepredictable network-on-chip to avoid the bottleneck of shared memory. We report our experiences and present results on the costs in terms of memory and execution time.

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Use of multicore processors in avionics systems and its potential impact on implementation and certification

Cited by 32 publications

References 1 publication

Timing Predictability in Future Multi-Core Avionics Systems

Timing Predictability in Future Multi-Core Avionics Systems

Safety Concept for a Mixed Criticality On-Board Software System ∗

Support for the logical execution time model on a time-predictable multicore processor

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