Use of selective precharge for low-power content-addressable memories

Zukowski, C.; Wang, Shaoyi

doi:10.1109/iscas.1997.621492

Cited by 80 publications

(40 citation statements)

References 5 publications

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“…This method divides the ML into two segments and evaluates only some of the upper bits of the word. In the case of the word matched by the upper bits, the remaining lower bits are evaluated [13]. However there are actually two overhead sources that limit power saving.…”

Section: Previously Techniquementioning

confidence: 99%

“…For the reasons, there have been many schemes to reduce the power consumption of the SL and ML at the circuit level. The previous methods to reduce the power consumption of the ML are low-swing scheme [11], selective precharge scheme [13], pipelining scheme [14], and current-saving scheme [17]. Furthermore, previous methods for reducing the power consumption of the SL include the eliminating SL precharge scheme [11], and hierarchical SL scheme [14 -15].…”

Section: Introductionmentioning

confidence: 99%

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Low-Power Ternary Content-Addressable Memory Using Power Reduction of Match-Line and Search-Line

Kim¹,

Kim²

2018

IJIES

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Abstract:The challenge to solve in large capacity ternary content addressable memory (TCAM) is the large power consumption of search-line and match-line. In this paper, we propose a circuit that uses match-line selectivecharging scheme and low-swing search-line scheme simultaneously to reduce power consumption of search-line and match-line which occupies a large ratio in power consumption of TCAM. The circuit was verified by Hspice simulation using a 1.8V supply voltage in a CMOS 0.18 um CMOS process. The proposed 128x128 bit TCAM shows 45.4% power savings in match-line and 74.7% power savings in search-line compared to the conventional precharge high scheme in search cycle. Also, the minimum search cycle time is 3 ns (333MHz).

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Section: Previously Techniquementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Low-Power Ternary Content-Addressable Memory Using Power Reduction of Match-Line and Search-Line

Kim¹,

Kim²

2018

IJIES

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“…The search-lines are switching to represent the new words to be compared and as a result match-lines are continuously switching based on the miss/match results. The AMchip04 design reduces power consumption in a significant way by using the pre-match power-saving technique [11].…”

Section: Vipram: Vertically Integrated Pattern Recognition Associativmentioning

confidence: 99%

Developement of 3D Vertically Integrated Pattern Recognition Associative Memory (VIPRAM)

Deputch¹,

Shochet²,

Lipton³

et al. 2011

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“…A static pseudo nmos CAM has been designed [4] which requires an extra pmos transistor for every CAM cell which use in it, so it is very bad idea to for each and every pmos for each stages. Other method has been designed which requires separate cmos parallel CAM for searching the data [5] which requires lot of area to implement it and also extra precharge device [6] to implement CAM. To overcome the disadvantages of the previous designs a Hybrid-Type CAM design [7] is proposed to improve the power, area and performance of the CAM cell.…”

Section: Introductionmentioning

confidence: 99%

"Low Power, Low Area and High Performance Hybrid Type Dynamic CAM Design"

Nagarjuna

Kittur

2011

IJCA

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Content-addressable memories (CAMs) are hardware search engines that are much faster than algorithmic approaches for search-intensive applications. CAMs are composed of conventional semiconductor memory (usually SRAM) with added comparison circuitry that enables a search operation to complete in a single clock cycle. In case of advanced applications we need large sized CAM but it has the disadvantage of high power consumption. To overcome the drawbacks we need to reduce the power consumption of the CAM when we search the data. This paper proposes an idea for improving power, area and performance of the system of recently proposed high Performance Hybrid-Type CAM Designs. For this we replace the basic 9T CAM cell with a 4T CAM cell. The simulation results show the success of the method.

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Use of selective precharge for low-power content-addressable memories

Cited by 80 publications

References 5 publications

Low-Power Ternary Content-Addressable Memory Using Power Reduction of Match-Line and Search-Line

Low-Power Ternary Content-Addressable Memory Using Power Reduction of Match-Line and Search-Line

Developement of 3D Vertically Integrated Pattern Recognition Associative Memory (VIPRAM)

"Low Power, Low Area and High Performance Hybrid Type Dynamic CAM Design"

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