Using adaptive routing to compensate for performance heterogeneity

Abstract

Scalable and power efficient multi-core architectures must be performance heterogeneous to accommodate semiconductor parametric variations and non-uniform access to shared resources. Due to its rate matching, a NoC on a Voltage-Frequency Island architecture can connect cores without forcing each one to give up its own operating point for the chip-wide common worst case. With run-time adaptive routing and task-to-core mapping, a NoC can run at the average not the worst case network saturation bandwidth. These run-time processes compensate for variations because they match application resource requirements with heterogeneous cores and routers.We focus on adaptive routing that simultaneously combats communication load imbalance from on-die variations and application topology. We show that even with static, fixed task-to-core mapping on multi-core architectures affected by stochastic variations, our MATC router increases the expected saturation bandwidth by 7-25% vs Dimension Order router. With systematic variations, the improvements are 5-50%. These gains compensate for saturation bandwidth degradation due to manufacturing variations and help to reduce design guard-bands.

Adaptive routing and Dynamic Frequency Scaling for NoC power-performance optimizations

“…However, such proposals can not adapt to run-time failure or traffic variations. The work in [9] presents an adaptive routing scheme to compensate for performance heterogeneity due to on-die variations or traffic imbalance. Another adaptive routing scheme is discussed in [10] with focus on global adaptive routing to overcome the suboptimal local adaptive ones.…”

“…Another adaptive routing scheme is discussed in [10] with focus on global adaptive routing to overcome the suboptimal local adaptive ones. However both [9] and [10] do not consider any impact on routing due to policies acting on frequency.…”

A3MAP: Architecture-Aware Analytic Mapping for Networks-on-Chip

“…2(d), interconnections between tile A and tile B or between tile C and tile F are unidirectional and tile D is not interconnected to tile E. Since the bandwidth of links is also different, its interconnection matrix is composed asymmetrically. This type of network is shown in VFI (Voltage Frequency Island) based NoC where each processor operates with own voltage and frequency and in NoC with faulty [14] and degraded links by process and temperature variation [13]. In case of a custom network, there is slightly difference in the composition of interconnection matrix.…”

“…The irregular mesh network can be also found in a regular mesh network when some links become faulty and degraded by process variation and temperature variation. After the fault and degradation of link are detected, task mapping and routing path allocation [13] should deal with the abnormal links and compensate for the loss of yield and performance. The previous task mapping algorithms make it inefficient to perform tasks in the irregular/custom network since they are not adaptive to the variation of network.…”