Using an Adaptive HPC Runtime System to Reconfigure the Cache Hierarchy

Totoni, Ehsan; Torrellas, Josep; Kalé, Laxmikant V.

doi:10.1109/sc.2014.90

Cited by 12 publications

(14 citation statements)

References 37 publications

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“…However, the benefits of using different levels of caches on application performance may not be proportional to their power consumption [43]. In our future work, we plan to add this additional degree of freedom to PARM, which is the ability to dynamically enable/disable caches at various levels.…”

Section: Discussionmentioning

confidence: 99%

Maximizing Throughput of Overprovisioned HPC Data Centers Under a Strict Power Budget

Sarood

Langer

Gupta

et al. 2014

SC14: International Conference for High Performance Computing, Networking, Storage and Analysis

105

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Abstract-Building future generation supercomputers while constraining their power consumption is one of the biggest challenges faced by the HPC community. For example, US Department of Energy has set a goal of 20 MW for an exascale (10 18 flops) supercomputer. To realize this goal, a lot of research is being done to revolutionize hardware design to build power efficient computers and network interconnects. In this work, we propose a software-based online resource management system that leverages hardware facilitated capability to constrain the power consumption of each node in order to optimally allocate power and nodes to a job. Our scheme uses this hardware capability in conjunction with an adaptive runtime system that can dynamically change the resource configuration of a running job allowing our resource manager to re-optimize allocation decisions to running jobs as new jobs arrive, or a running job terminates.We also propose a performance modeling scheme that estimates the essential power characteristics of a job at any scale. The proposed online resource manager uses these performance characteristics for making scheduling and resource allocation decisions that maximize the job throughput of the supercomputer under a given power budget. We demonstrate the benefits of our approach by using a mix of jobs with different powerresponse characteristics. We show that with a power budget of 4.75 MW, we can obtain up to 5.2X improvement in job throughput when compared with the SLURM scheduling policy that is power-unaware. We corroborate our results with real experiments on a relatively small scale cluster, in which we obtain a 1.7X improvement.

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Section: Discussionmentioning

confidence: 99%

Maximizing Throughput of Overprovisioned HPC Data Centers Under a Strict Power Budget

Sarood

Langer

Gupta

et al. 2014

SC14: International Conference for High Performance Computing, Networking, Storage and Analysis

105

View full text Add to dashboard Cite

show abstract

“…Cache reconfiguration has been proposed to save power consumption by turning off cache banks that are not in use, which is promising for non-data-intensive applications. Using software methods to reconfigure cache has been investigated for the runtime system [Totoni et al 2014b] and compiler (Tavarageri and Sadayappan 2013). To decrease the energy consumed by moving data in the application layer, increasing data locality is critical.…”

Section: Power Consumption and Managementmentioning

confidence: 99%

A survey on software methods to improve the energy efficiency of parallel computing

Jin

Supinski

Abramson

et al. 2016

The International Journal of High Performance Computing Applica

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Energy consumption is one of the top challenges for achieving the next generation of supercomputing. Codesign of hardware and software is critical for improving energy efficiency (EE) for future large-scale systems. Many architectural power-saving techniques have been developed, and most hardware components are approaching physical limits. Accordingly, parallel computing software, including both applications and systems, should exploit power-saving hardware innovations and manage efficient energy use. In addition, new power-aware parallel computing methods are essential to decrease energy usage further. This article surveys software-based methods that aim to improve EE for parallel computing. It reviews the methods that exploit the characteristics of parallel scientific applications, including load imbalance and mixed precision of floating-point (FP) calculations, to improve EE. In addition, this article summarizes widely used methods to improve power usage at different granularities, such as the whole system and per application. In particular, it describes the most important techniques to measure and to achieve energy-efficient usage of various parallel computing facilities, including processors, memories, and networks. Overall, this article reviews the state-of-the-art of energy-efficient methods for parallel computing to motivate researchers to achieve optimal parallel computing under a power budget constraint.

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“…While (at least to date) many codes follow a simple Single Program Multiple Data (SPMD) approach where multiple cores execute the same code several times, even more complex patterns, different repetitions of loops that iterate over similar sets of data several times produce similar execution patterns. As a consequence, codes almost always exhibit a certain degree of repetitive behavior that can be observed either over time or by considering the logical execution structure, which is composed of event sequences [20,33,7]. This iterative nature of parallel applications allows us to effectively guide the whole application behavior by observing only small but significant portions of the parallel execution.…”

Section: Exploiting Application Structurementioning

confidence: 99%

Runtime-Guided Mitigation of Manufacturing Variability in Power-Constrained Multi-Socket NUMA Nodes

Chasapis

Casas

Moretó

et al. 2016

Proceedings of the 2016 International Conference on Supercomputing

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Current large scale systems show increasing power demands, to the point that it has become a huge strain on facilities and budgets. Researchers in academia, labs and industry are focusing on dealing with this "power wall", striving to find a balance between performance and power consumption. Some commodity processors enable power capping, which opens up new opportunities for applications to directly manage their power behavior at user level. However, while power capping ensures a system will never exceed a given power limit, it also leads to a new form of heterogeneity: natural manufacturing variability, which was previously hidden by varying power to achieve homogeneous performance, now results in heterogeneous performance caused by different CPU frequencies, potentially for each core, to enforce the power limit.In this work we show how a parallel runtime system can be used to effectively deal with this new kind of performance heterogeneity by compensating the uneven effects of power capping. In the context of a NUMA node composed of several multi-core sockets, our system is able to optimize the energy and concurrency levels assigned to each socket to maximize performance. Applied transparently within the parallel runtime system, it does not require any programmer interaction like changing the application source code or manually reconfiguring the parallel system. We compare our novel runtime analysis with an offline approach and demonstrate that it can achieve equal performance at a fraction of the cost.ACM acknowledges that this contribution was authored or co-authored by an employee, or contractor of the national government. As such, the Government retains a nonexclusive, royalty-free right to publish or reproduce this article, or to allow others to do so, for Government purposes only. Permission to make digital or hard copies for personal or classroom use is granted. Copies must bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. To copy otherwise, distribute, republish, or post, requires prior specific permission and/or a fee. Request permissions from permissions@acm.org.

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Using an Adaptive HPC Runtime System to Reconfigure the Cache Hierarchy

Cited by 12 publications

References 37 publications

Maximizing Throughput of Overprovisioned HPC Data Centers Under a Strict Power Budget

Maximizing Throughput of Overprovisioned HPC Data Centers Under a Strict Power Budget

A survey on software methods to improve the energy efficiency of parallel computing

Runtime-Guided Mitigation of Manufacturing Variability in Power-Constrained Multi-Socket NUMA Nodes

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