Using Bypass to Tighten WCET Estimates for Multi-Core Processors with Shared Instruction Caches

Hardy, Damien; Piquet, Thomas; Puaut, Isabelle

doi:10.1109/rtss.2009.34

Cited by 61 publications

(53 citation statements)

References 28 publications

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“…In [13], task lifetime information is computed and utilized to refine possible interferences. In [7], a method for identifying and bypassing the static single usage memory blocks so as to reduce the number of interferences is proposed. In [15], abstract interpretation based cache analysis is combined with model checking based bus analysis to achieve more precise interference analysis.…”

Section: Discussionmentioning

confidence: 99%

Top-down and bottom-up multi-level cache analysis for WCET estimation

Zhang

Koutsoukos

2015

21st IEEE Real-Time and Embedded Technology and Applications Symposium

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Abstract-In many multi-core architectures, inclusive shared caches are used to reduce cache coherence complexity. However, the enforcement of the inclusion property can cause invalidation of memory blocks at higher cache levels. In order to ensure safety, analysis of cache hierarchies with inclusive caches for worst-case execution time (WCET) estimation is typically based on conservative decisions. Thus, the estimation may not be tight. In order to tighten the estimation, this paper proposes an approach that can more precisely analyze the behavior of a cache hierarchy maintaining the inclusion property. We illustrate the approach in the context of multi-level instruction caches. The approach first analyzes all the inclusive caches in the hierarchy in a bottom-up direction, and then analyzes the remaining non-inclusive caches in a top-down direction. In order to capture the inclusion victims and their effects, we also propose a concept of aging barrier and integrate it with the traditional must and persistence analyses to safely slow down their aging process so as to derive more precise analyses. We evaluate the proposed approach on a set of benchmarks and the evaluation reveals that the estimations are tightened.

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Section: Discussionmentioning

confidence: 99%

Top-down and bottom-up multi-level cache analysis for WCET estimation

Zhang

Koutsoukos

2015

21st IEEE Real-Time and Embedded Technology and Applications Symposium

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“…The work in this paper is orthogonal to many existing proposals that reduce WCET such as compilation optimization [10]- [12] and cache locking mechanism [13]. And it is different from existing task scheduling and mapping work in three aspects.…”

Section: Related Workmentioning

confidence: 99%

Cache-Aware Cooperative Task Mapping in Multi-core Real-Time Systems

Wang¹,

Ni²,

Jicheng³

et al. 2016

IJIEE

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Abstract-Program execution can be accelerated with efficient use of cache in real-time systems. And each program has its own instruction access pattern, which causes uneven distribution of accesses to the sets of instruction cache. In multi-core real-time systems, mapping tasks with similar instruction access patterns to the same core will incur massive conflicts and degrade the utilization of the cache. This paper proposes a cache-aware cooperative task mapping method to improve system efficiency in multi-core real-time systems. Our method quantifies the access frequency of instruction cache sets for each task, and then select tasks with complementary distributions to run on the same core, which can reduce inter-task interference and shorten the cache refill delay during context switch. Evaluation results show that the utilization of the system is improved by about 8.92% with the method.

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“…For example, results on intrinsic cache analysis and WCET estimation [14] can be used as an input to our analysis; studies on cache-related preemption and migration delay [4] can be used to obtain the value of ∆ crpmd used in our analysis; and finally, cache-aware scheduling, such as [13], can be used to reduce the additional cache-related overhead in the compositional/virtualization setting.…”

Section: Related Workmentioning

confidence: 99%

Cache-aware compositional analysis of real-time multicore virtualization platforms

Phan

Sokolsky

et al. 2015

Real-Time Syst

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Multicore processors are becoming ubiquitous, and it is becoming increasingly common to run multiple realtime systems on a shared multicore platform. While this trend helps to reduce cost and to increase performance, it also makes it more challenging to achieve timing guarantees and functional isolation.One approach to achieving functional isolation is to use virtualization. However, virtualization also introduces many challenges to the multicore timing analysis; for instance, the overhead due to cache misses becomes harder to predict, since it depends not only on the direct interference between tasks but also on the indirect interference between virtual processors and the tasks executing on them.In this paper, we present a cache-aware compositional analysis technique that can be used to ensure timing guarantees of components scheduled on a multicore virtualization platform. Our technique improves on previous multicore compositional analyses by accounting for the cache-related overhead in the components' interfaces, and it addresses the new virtualization-specific challenges in the overhead analysis. To demonstrate the utility of our technique, we report results from an extensive evaluation based on randomly generated workloads. Abstract-Multicore processors are becoming ubiquitous, and it is becoming increasingly common to run multiple real-time systems on a shared multicore platform. While this trend helps to reduce cost and to increase performance, it also makes it more challenging to achieve timing guarantees and functional isolation.One approach to achieving functional isolation is to use virtualization. However, virtualization also introduces many challenges to the multicore timing analysis; for instance, the overhead due to cache misses becomes harder to predict, since it depends not only on the direct interference between tasks but also on the indirect interference between virtual processors and the tasks executing on them.In this paper, we present a cache-aware compositional analysis technique that can be used to ensure timing guarantees of components scheduled on a multicore virtualization platform. Our technique improves on previous multicore compositional analyses by accounting for the cache-related overhead in the components' interfaces, and it addresses the new virtualizationspecific challenges in the overhead analysis. To demonstrate the utility of our technique, we report results from an extensive evaluation based on randomly generated workloads.

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Using Bypass to Tighten WCET Estimates for Multi-Core Processors with Shared Instruction Caches

Cited by 61 publications

References 28 publications

Top-down and bottom-up multi-level cache analysis for WCET estimation

Top-down and bottom-up multi-level cache analysis for WCET estimation

Cache-Aware Cooperative Task Mapping in Multi-core Real-Time Systems

Cache-aware compositional analysis of real-time multicore virtualization platforms

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