Using design based binning to improve defect excursion control for 45nm production

Huang, Chia Wei; Young, Chris; Liu, H.; Tzou, S.F.; Tsui, David; Tsai, Alex; Chang, Ellis

doi:10.1109/issm.2007.4446790

Cited by 13 publications

(10 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Layout snippets 1 containing these hotspots are extracted and clustered with the goal of formulating DFM rules. Lastly, the work described in [22,23] extracts layout features (such as the number of vertices in a polygon, minimum-line width and spacing, etc.) of suspect defect locations identified by bright-field inspection.…”

Section: A Prior Workmentioning

confidence: 99%

“…The work in [22,23] also closely resembles LASIC but again there are several subtle but important differences: First, LASIC analyzes layout images while the approach in [22,23] extracts user-defined layout features. In other words, LASIC makes no assumption on the importance of certain layout features but instead automatically discovers the important layout features.…”

Section: B Our Contributionmentioning

confidence: 99%

See 1 more Smart Citation

LASIC: Layout Analysis for Systematic IC-Defect Identification Using Clustering

Tam

Blanton

2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

Section: A Prior Workmentioning

confidence: 99%

Section: B Our Contributionmentioning

confidence: 99%

LASIC: Layout Analysis for Systematic IC-Defect Identification Using Clustering

Tam

Blanton

2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

“…Lastly, the work described in [85,86] extracts layout features (such as the number of vertices in a polygon, minimum-line width and spacing, etc.) of suspect defect locations identified by bright-field inspection.…”

Section: Prior Workmentioning

confidence: 99%

“…The work in [85,86] also closely resembles LASIC but again there are several subtle but important differences: First, LASIC analyzes layout images while the approach in [85,86] extracts user-defined layout features. In other words, LASIC makes no assumption on the importance of certain layout features but instead automatically discovers the important layout features.…”

Section: Our Contributionmentioning

confidence: 99%

“…Third, a vast number of image processing techniques are immediately available for analysis of layout images. Finally, the work in [85,86] uses bright-field inspection to find potential defect locations, but these locations have not yet been shown to cause failure, which results in another source of uncertainty. LASIC instead uses diagnosis-implicated regions that are generated by diagnosing actual ICs that are known to have failed.…”

Section: Our Contributionmentioning

confidence: 99%

See 1 more Smart Citation

Physically-Aware Analysis of Systematic Defects in Integrated Circuits

Tam¹,

Blanton

2012

IEEE Des. Test. Comput.

View full text Add to dashboard Cite

In the integrated circuit (IC) industry, all products must go through three phases before they are available in the market, namely design, manufacturing, and testing. Design, obviously, refers to the process of converting the early concepts of the product into a precise description of its implementation. Manufacturing then uses this description to fabricate the product, where the design is physically materialized onto the silicon wafer and later packaged into the product. If design and manufacturing are perfect, then every fabricated IC is completely functional, thereby obliterating the need for testing. Unfortunately, both design and manufacturing are not ideal; therefore every manufactured IC must be subject to stringent testing procedures to ensure that most bad ICs are identified and prevented from shipping to the end-users.ICs are deemed bad when they contain certain defects that cause the ICs to fail the specifications.Defects are unintended structural and/or material changes of the IC due to design/manufacturing imperfections.These physical changes may alter the electrical characteristics of the circuit, which are sometimes severe enough to lead to a failure (i.e., violation of one or more design specifications). Common defects in IC manufacturing can be caused by contaminations in the process, variations of the process conditions, or simply the difficulty to fabricate certain features of the design. The last issue is the focus of this dissertation. Defects that arise due to certain aspects of the design being sensitive to the manufacturing process with an elevated likelihood of failure are known as systematic defects. This dissertation addresses the issues related to the prevention and identification of systematic defects by analyzing a large amount of manufactured ICs that have failed testing.For systematic-defect prevention, one common approach is to use design-for-manufacturability (DFM) rules to communicate hard-to-manufacture features to designers so that these features can be minimized in the iii design. Obviously, different rules describe different features and thus their violation/adherence will have different impact on the manufacturability of the product. It is therefore desirable to measure the relative importance of the rules and how they affect product yield. To address this issue, a method called RADAR (Rule Assessment of Defect-Affected Regions) has been developed for measuring the effectiveness of DFM rules in preventing systematic defects. RADAR analyzes a large amount of test data of failed ICs to draw statistical conclusion.Taking preventive measures, such as enforcing DFM rules, is necessary to ensure sufficient product yield. Unfortunately, the amount of resource (circuit area, designer's time, etc.) dedicated to DFM can be quite limited. It is therefore impractical to anticipate and prevent every possible hard-to-manufacture design features before the product is manufactured. Thus, systematic defects can still exist. Therefore, a mechanism is required to identify systematic ...

show abstract

Lithography technology for advanced devices and introduction to integrated CAD analysis for hotspot detection

Vikram

Agarwal

2017

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

Optical projection lithography has been the workhorse of the integrate circuit (IC) manufacturing industry to transfer the computer-aided design (CAD) to semiconducting material wafers. The resolution limit of the 193 nm wavelength lithography which was initially targeted for the 90 nm design rule has been further extended to realise ∼10-20 nm devices with ingenious interventions. The three-dimensional fin-shaped field-effect transistor device structure now realise the <20 nm design rule still using 193 nm projection lithography as the widely accepted solution. The extreme ultraviolet wavelength source systems are still in development and testing phases with some recent success reported, but still falling short of supporting volume production requirements. This study reviews the current trends in lithography and the associated resolution enhancement techniques with brief introduction to an integrated CAD analysis for hotspot detection.

show abstract

Using design based binning to improve defect excursion control for 45nm production

Cited by 13 publications

References 4 publications

LASIC: Layout Analysis for Systematic IC-Defect Identification Using Clustering

LASIC: Layout Analysis for Systematic IC-Defect Identification Using Clustering

Physically-Aware Analysis of Systematic Defects in Integrated Circuits

Lithography technology for advanced devices and introduction to integrated CAD analysis for hotspot detection

Contact Info

Product

Resources

About