Using Functional Programming to Generate an LDPC Forward Error Corrector

Gill, Andy; Bull, Tristan; DePardo, Dan; Farmer, Andrew; Komp, Ed; Perrins, Erik

doi:10.1109/fccm.2011.31

Cited by 6 publications

(4 citation statements)

References 17 publications

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“…FCUDA transforms a CUDA kernel into a C function annotated with AutoPilot directives and then uses AutoPilot to generate synthesizable HDL. Recent publications propose using GPUs to perform LDPC decoding [Falcao et al 2011] or functional programming to target LDPC codes in FPGAs [Gill et al 2011;Smith et al 2011].…”

Section: Related Workmentioning

confidence: 99%

Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs

Owaida¹,

Falcão

Andrade

et al. 2015

ACM Trans. Embed. Comput. Syst.

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The design cycle for complex special-purpose computing systems is extremely costly and time-consuming. It involves a multiparametric design space exploration for optimization, followed by design verification. Designers of special purpose VLSI implementations often need to explore parameters, such as optimal bitwidth and data representation, through time-consuming Monte Carlo simulations. A prominent example of this simulation-based exploration process is the design of decoders for error correcting systems, such as the Low-Density Parity-Check (LDPC) codes adopted by modern communication standards, which involves thousands of Monte Carlo runs for each design point. Currently, high-performance computing offers a wide set of acceleration options that range from multicore CPUs to Graphics Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs). The exploitation of diverse target architectures is typically associated with developing multiple code versions, often using distinct programming paradigms. In this context, we evaluate the concept of retargeting a single OpenCL program to multiple platforms, thereby significantly reducing design time. A single OpenCL-based parallel kernel is used without modifications or code tuning on multicore CPUs, GPUs, and FPGAs. We use SOpenCL (Silicon to OpenCL), a tool that automatically converts OpenCL kernels to RTL in order to introduce FPGAs as a potential platform to efficiently execute simulations coded in OpenCL. We use LDPC decoding simulations as a case study. Experimental results were obtained by testing a variety of regular and irregular LDPC codes that range from short/medium (e.g., 8,000 bit) to long length (e.g., 64,800 bit) DVB-S2 codes. We observe that, depending on the design parameters to be simulated, on the dimension and phase of the design, the GPU or FPGA may suit different purposes more conveniently, thus providing different acceleration factors over conventional multicore CPUs.

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Section: Related Workmentioning

confidence: 99%

Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs

Owaida¹,

Falcão

Andrade

et al. 2015

ACM Trans. Embed. Comput. Syst.

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“…We make critical use of the ability to generate VHDL provided by Kansas Lava, and the Xilinx XST toolkit to generate bit files for FPGA reprogramming. Gill et al (2011) presents the FPGAspecific details of deploying our generated LDPC implementation, including board-specific challenges and data transportation issues. Given the common LDPC artifact, there is overlap between Gill et al (2011) and this paper.…”

Section: Related Workmentioning

confidence: 99%

“…Gill et al (2011) presents the FPGAspecific details of deploying our generated LDPC implementation, including board-specific challenges and data transportation issues. Given the common LDPC artifact, there is overlap between Gill et al (2011) and this paper. Specifically, the generic description of the LDPC algorithm in Section 6, and the high-level description of our fabric partitioning aspect at the start of Section 7 were both adapted from the descriptions in the earlier paper.…”

Section: Related Workmentioning

confidence: 99%

Deriving an efficient FPGA implementation of a low density parity check forward error corrector

Gill¹,

Farmer²

2011

Proceedings of the 16th ACM SIGPLAN International Conference on Functional Programming

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Creating correct hardware is hard. Though there is much talk of using formal and semi-formal methods to develop designs and implementations, in practice most implementations are written without the support of any formal or semi-formal methodology. Having such a methodology brings many benefits, including improved likelihood of a correct implementation, lowering the cost of design exploration and lowering the cost of certification. In this paper, we introduce a semi-formal methodology for connecting executable specifications written in the functional language Haskell to efficient VHDL implementations. The connection is performed by manual edits, using semi-formal equational reasoning facilitated by the worker/wrapper transformation, and directed using commutable functors. We explain our methodology on a full-scale example, an efficient Low-Density Parity Check forward error correcting code, which has been implemented on a Virtex-5 FPGA.

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“…Also, recent publications propose using GPUs to perform LDPC decoding [1] or functional programming to target LDPC codes in FPGAs [17], but still none of these approaches provide a unique solution that is suitable to target at the same time CPU, GPU and FPGA architectures. In this paper, our objective is to simplify the exploration of all three target architectures using a single unified programming model that allows extracting the most interesting properties of each.…”

Section: Related Workmentioning

confidence: 99%

Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case

Falcão

Owaida

Novo

et al. 2012

2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines

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Abstract-Hardware designers and engineers typically need to explore a multi-parametric design space in order to find the best configuration for their designs using simulations that can take weeks to months to complete. For example, designers of special purpose chips need to explore parameters such as the optimal bitwidth and data representation. This is the case for the development of complex algorithms such as Low-Density Parity-Check (LDPC) decoders used in modern communication systems. Currently, high-performance computing offers a wide set of acceleration options, that range from multicore CPUs to graphics processing units (GPUs) and FPGAs. Depending on the simulation requirements, the ideal architecture to use can vary. In this paper we propose a new design flow based on OpenCL, a unified multiplatform programming model, which accelerates LDPC decoding simulations, thereby significantly reducing architectural exploration and design time. OpenCL-based parallel kernels are used without modifications or code tuning on multicore CPUs, GPUs and FPGAs. We use SOpenCL (Silicon to OpenCL), a tool that automatically converts OpenCL kernels to RTL for mapping the simulations into FPGAs. To the best of our knowledge, this is the first time that a single, unmodified OpenCL code is used to target those three different platforms. We show that, depending on the design parameters to be explored in the simulation, on the dimension and phase of the design, the GPU or the FPGA may suit different purposes more conveniently, providing different acceleration factors. For example, although simulations can typically execute more than 3× faster on FPGAs than on GPUs, the overhead of circuit synthesis often outweighs the benefits of FPGA-accelerated execution.

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Using Functional Programming to Generate an LDPC Forward Error Corrector

Cited by 6 publications

References 17 publications

Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs

Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs

Deriving an efficient FPGA implementation of a low density parity check forward error corrector

Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case

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