Using live sequence charts for hardware protocol specification and compliance verification

Verification of present day SoCs is proving to be challenging due to complex interactions among various subcomponents and IPs, with multiple clock domains and diverse bus protocols. The quality of verification depends on the precision in specifying the interaction behaviors. We propose a visual specification language called CESC (Clocked Event Sequence Chart), designed to specify interaction scenarios in SoCs. CESC provides a unique mechanism for representating multiple clock domains, based upon which event occurrences and interactions among different subcomponents can be represented. CESC has a pictorial and textual syntax, and a formal semantics to enable rigorous analysis. The semantics is based on standard notions of partial ordering and timed event traces. CESC is useful in many ways in formalizing SoC verification flows, namely, formalization of verification scenarios, synthesis of protocol checkers and consistency checking of specification versus implementation. This paper describes an algorithm to translate CESC scenarios to protocol checkers used in SoC verification flow. A few examples from industrial designs are included to illustrate the applicability of this formalism in specifying bus transactions and properties of protocols.

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“…Earlier, a preliminary application of an MSC variant in specification of hardware protocols has been attempted in [8].…”

Section: Discussionmentioning

confidence: 99%

Cesc

Gadkari

Ramesh

Parekhji

2004

Proceedings of the 14th ACM Great Lakes Symposium on VLSI

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“…This formalization challenge can be surmounted by introducing into the language a notation for conditions, and then by defining a semantics for these conditions. A closer study of these issues is presented elsewhere [Bunker and Gopalakrishnan 2001].…”

Section: Message Sequence Charts the International Telecommunicationmentioning

confidence: 99%

Formal hardware specification languages for protocol compliance verification

Bunker

Gopalakrishnan

McKee

2004

ACM Trans. Des. Autom. Electron. Syst.

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The advent of the system-on-chip and intellectual property hardware design paradigms makes protocol compliance verification increasingly important to the success of a project. One of the central tools in any verification project is the modeling language, and we survey the field of candidate languages for protocol compliance verification, limiting our discussion to languages originally intended for hardware and software design and verification activities. We frame our comparison by first constructing a taxonomy of these languages, and then by discussing the applicability of each approach to the compliance verification problem. Each discussion includes a summary of the development of the language, an evaluation of the language's utility for our problem domain, and, where feasible, an example of how the language might be used to specify hardware protocols. Finally, we make some general observations regarding the languages considered.

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“…Reference [14] uses statemate and LSCs to capture the critical communication protocols in the train system. In [15] [16], the authors propose using Live Sequence Charts to specify hardware standards. In [17] LSCs are used to specify the complex behaviors among multi Web services.…”

Section: A Tool-plsc Editormentioning

confidence: 99%

A requirements description language pLSC for probabilistic branches and three-stage events

Kai

Miao

Gao

2014

15th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed C

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The language of Live Sequence Chart (LSC), a multi-modal extension of MSC, introduces the distinction between mandatory and possible on the level of the whole chart and for the chart elements. While the LSC still extend the MSC qualitatively, when it comes to capturing the quantitative behaviors, the deficiency emerges. As for the probabilistic systems, i.e., systems that exhibit probabilistic aspects, probabilistic properties are considered as the most important requirements and need to be captured quantitatively. To address this, we propose a requirements description language called pLSC. Supported by the measure theory and the probability theory, the language pLSC describes the interactions quantitatively to suit the probabilistic systems from two dimensions of probabilistic branches and three-stage events. The paper introduces the graphical and textual presentation of the pLSC.

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Using live sequence charts for hardware protocol specification and compliance verification

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Cited by 10 publications

References 9 publications

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Formal hardware specification languages for protocol compliance verification

A requirements description language pLSC for probabilistic branches and three-stage events

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