Using Run-Time Reconfiguration to Implement Fault-Tolerant Coarse Grained Reconfigurable Architectures

Schweizer, T.; Küster, Anja; Eisenhardt, Sven; Kuhn, Tommy

doi:10.1109/ipdpsw.2012.39

Cited by 10 publications

(4 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The FEHM monitors data to detect and mask permanent, transient and timing faults. Based on the FEHM we developed our low-cost TMR strategy [20] for CGRAs. Traditional TMR allows error detection and error masking.…”

Section: Low-cost Tmrmentioning

confidence: 99%

“…This work is part of the DFG funded priority program SPP 1500 "Dependable Embedded Systems"¹. The paper covers three projects related to system-and hardwarearchitecture, namely VirTherm-3D (system-level task mapping and communication) [12][13][14], OTERA (FGRP) [15][16][17], and ARES (CGRA) [18][19][20][21]. It is part of the IT special issue on "Embedded Systems".…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Adaptive multi-layer techniques for increased system dependability

Bauer

Henkel

Herkersdorf

et al. 2015

It - Information Technology

Self Cite

View full text Add to dashboard Cite

Achieving system-level dependability is a demanding task. The manifold requirements and dependability threats can no longer be statically addressed at individual abstraction layers. Instead, all components of future multi-processor systems-on-chip (MPSoCs) have to contribute to this common goal in an adaptive manner. In this paper we target a generic heterogeneous MPSoC that combines general purpose processors along with dedicated application-specific hard-wired accelerators, finegrained reconfigurable processors, and coarse-grained reconfigurable architectures. We present different reactive and proactive measures at the layers of the runtime system (online resource management), system architecture (global communication), micro architecture (individual tiles), and gate netlist (tile-internal circuits) to address dependability threats.

show abstract

Section: Low-cost Tmrmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Adaptive multi-layer techniques for increased system dependability

Bauer

Henkel

Herkersdorf

et al. 2015

It - Information Technology

Self Cite

View full text Add to dashboard Cite

show abstract

“…By mapping these components into the temporal domain, they are deliberately slowed-down by the factor s to only calculate as many samples as are absolutely required to have detection latency DL, the time from fault occurrence to fault detection, meet the deadline with the desired confidence. The usage of fault tolerant CGRAs [31] ensures that the information thereby acquired is reliable.…”

Section: Architectural Layer Examplementioning

confidence: 99%

Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience

Herkersdorf

Aliee

Engel

et al. 2014

Microelectronics Reliability

Self Cite

View full text Add to dashboard Cite

The Resilience Articulation Point (RAP) model aims at provisioning researchers and developers with a probabilistic fault abstraction and error propagation framework covering all hardware/software layers of a System on Chip. RAP assumes that physically induced faults at the technology or CMOS device layer will eventually manifest themselves as a single or multiple bit flip(s). When probabilistic error functions for specific fault origins are known at the bit or signal level, knowledge about the unit of design and its environment allow the transformation of the bit-related error functions into characteristic higher layer representations, such as error functions for data words, Finite State Machine (FSM) state, macro-interfaces or software variables. Thus, design concerns at higher abstraction layers can be investigated without the necessity to further consider the full details of lower levels of design. This paper introduces the ideas of RAP based on examples of radiation induced soft errors in SRAM cells, voltage variations and sequential CMOS logic. It shows by example how probabilistic bit flips are systematically abstracted and propagated towards higher abstraction levels up to the application software layer, and how RAP can be used to parameterize architecture-level resilience methods. AbstractThe Resilience Articulation Point (RAP) model aims at provisioning researchers and developers with a probabilistic fault abstraction and error propagation framework covering all hardware/software layers of a System on Chip. RAP assumes that physically induced faults at the technology or CMOS device layer will eventually manifest themselves as a single or multiple bit flip(s). When probabilistic error functions for specific fault origins are known at the bit or signal level, knowledge about the unit of design and its environment allow the transformation of the bit-related error functions into characteristic higher layer representations, such as error functions for data words, Finite State Machine (FSM) state, macro interfaces or software variables. Thus, design concerns at higher abstraction layers can be investigated without the necessity to further consider the full details of lower levels of design. This paper introduces the ideas of RAP based on examples of radiation induced soft errors in SRAM cells, voltage variations and sequential CMOS logic. It shows by example how probabilistic bit flips are systematically abstracted and propagated towards higher abstraction levels up to the application software layer, and how RAP can be used to parameterize architecture-level resilience methods.

show abstract

“…The fact that spatial/temporal redundancy is required for increased reliability is well established. However, the architectural benefits of reconfigurable processor from the perspective of reliability are still to be understood [132].…”

Section: Novel Late-cmos and Post-cmos Architecturesmentioning

confidence: 99%

Ingredients of Adaptability: A Survey of Reconfigurable Processors

Chattopadhyay

2013

VLSI Design

View full text Add to dashboard Cite

For a design to survive unforeseen physical effects like aging, temperature variation, and/or emergence of new application standards, adaptability needs to be supported. Adaptability, in its complete strength, is present in reconfigurable processors, which makes it an important IP in modern System-on-Chips (SoCs). Reconfigurable processors have risen to prominence as a dominant computing platform across embedded, general-purpose, and high-performance application domains during the last decade. Significant advances have been made in many areas such as, identifying the advantages of reconfigurable platforms, their modeling, implementation flow and finally towards early commercial acceptance. This paper reviews these progresses from various perspectives with particular emphasis on fundamental challenges and their solutions. Empowered with the analysis of past, the future research roadmap is proposed.

show abstract

Using Run-Time Reconfiguration to Implement Fault-Tolerant Coarse Grained Reconfigurable Architectures

Cited by 10 publications

References 8 publications

Adaptive multi-layer techniques for increased system dependability

Adaptive multi-layer techniques for increased system dependability

Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience

Ingredients of Adaptability: A Survey of Reconfigurable Processors

Contact Info

Product

Resources

About