Using statistical models with duplication and compare for reduced cost FPGA reliability

Anderson, Jon-Paul; Nelson, Brent; Wirthlin, Michael

doi:10.1109/aero.2010.5446660

Cited by 5 publications

(2 citation statements)

References 6 publications

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“…Since this can be implemented in multiple ways, such as adding an additional voting circuit [31] or in a time multiplexed manner [32] (with different costs), in order not to lose generality, the approach in this paper will assume that the cost of nredundancy is the hardware cost of the n−1 additional replicas of the task. On the other hand, double redundancy, also known as DWC, has also been investigated as an alternative to TMR since it reduces the area overhead of triplication [33], [34]. Finally, the example of Figure 5 achieves a reliability improvement and a makespan degradation between those of Figure 3 and Figure 4.…”

Section: Motivational Examplementioning

confidence: 99%

Reliability and Makespan Optimization of Hardware Task Graphs in Partially Reconfigurable Platforms

Ramezani

Sedaghat

Naghibzadeh

et al. 2017

IEEE Trans. Aerosp. Electron. Syst.

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Abstract-This paper addresses the problem of reliability and makespan optimization of hardware task graphs in reconfigurable platforms by applying fault tolerance (FT) techniques to the running tasks based on the exploration of the Pareto set of solutions. In the presented solution, in contrast to existing approaches in the literature, task graph scheduling, tasks parallelism, reconfiguration delay, and FT requirements are taken into account altogether. This paper firstly presents a model for hardware task graphs, task prefetch and scheduling, reconfigurable computer and a fault model for reliability. Then, a mathematical model of an integer nonlinear multi-objective optimization problem is presented for improving the FT of hardware task graphs, scheduled in partially reconfigurable platforms. Experimental results show the positive impacts of choosing the FT techniques selected by the proposed solution, which is named Pareto-based. Thus, in comparison to non-fault-tolerant designs or other stateof-the-art FT approaches, without increasing makespan, about 850% Mean Time To Failure (MTTF) improvement is achieved and, without degrading reliability, makespan is improved by 25%. In addition, experiments in fault-varying environments have demonstrated that the presented approach outperforms existing state-of-the-art adaptive FT techniques in terms of both MTTF and makespan.

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Section: Motivational Examplementioning

confidence: 99%

Reliability and Makespan Optimization of Hardware Task Graphs in Partially Reconfigurable Platforms

Ramezani

Sedaghat

Naghibzadeh

et al. 2017

IEEE Trans. Aerosp. Electron. Syst.

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“…200% hardware overhead. An extension to DWC is proposed by Anderson et al in [Anderson et al 2010]. The authors use DWC as failure masking technique by taking advantage of the probabilistic distribution of a circuit's output.…”

Section: User Logicmentioning

confidence: 99%

Mitigation of Radiation Effects in SRAM-Based FPGAs for Space Applications

Siegle

Vladimirova

Ilstad³

et al. 2015

ACM Comput. Surv.

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The use of static random access memory (SRAM)-based field programmable gate arrays (FPGAs) in harsh radiation environments has grown in recent years. These types of programmable devices require special mitigation techniques targeting the configuration memory, the user logic, and the embedded RAM blocks. This article provides a comprehensive survey of the literature published in this rich research field during the past 10 years. Furthermore, it can also serve as a tutorial for space engineers, scientists, and decision makers who need an introduction to this topic.

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