Utilizing Dark Silicon to Save Energy with Computational Sprinting

Raghavan, Arun; Emurian, Laurel; Shao, Li; Papaefthymiou, Marios C.; Pipe, Kevin P.; Wenisch, Thomas F.; Martin, Milo M. K.

doi:10.1109/mm.2013.76

Cited by 32 publications

(10 citation statements)

References 9 publications

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“…Our technique targets improving sustained chip throughput, rather than improving interactive responsiveness. Raghavan et al [2013a] show that computational sprinting can also be beneficial for sustained performance if enabling more cores leads to a better energy efficiency. In a heterogeneous multicore setup, we find that a sprint-and-rest scheme (run on the big core, and then idle; the second technique in Figure 2) never outperforms a sprint-and-walk scheme (run on the big core, followed by running on the little core), because running on the little core is always more energy-efficient than running on the big core.…”

Section: Power and Thermal Managementmentioning

confidence: 99%

Maximizing Heterogeneous Processor Performance Under Power Constraints

Adileh

Eyerman²,

Jaleel

et al. 2016

ACM Trans. Archit. Code Optim.

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Heterogeneous processors (e.g., ARM's big.LITTLE) improve performance in power-constrained environments by executing applications on the 'little' low-power core and move them to the 'big' high-performance core when there is available power budget. The total time spent on the big core depends on the rate at which the application dissipates the available power budget. When applications with different big-core power consumption characteristics concurrently execute on a heterogeneous processor, it is best to give a larger share of the power budget to applications that can run longer on the big core, and a smaller share to applications that run for a very short duration on the big core.This article investigates mechanisms to manage the available power budget on power-constrained heterogeneous processors. We show that existing proposals that schedule applications onto a big core based on various performance metrics are not high performing, as these strategies do not optimize over an entire power period and are unaware of the applications' power/performance characteristics. We use linear programming to design the DPDP power management technique, which guarantees optimal performance on heterogeneous processors. We mathematically derive a metric (Delta Performance by Delta Power) that takes into account the power/performance characteristics of each running application and allows our power-management technique to decide how best to distribute the available power budget among the co-running applications at minimal overhead. Our evaluations with a 4-core heterogeneous processor consisting of big.LITTLE pairs show that DPDP improves performance by 16% on average and up to 40% compared to a strategy that globally and greedily optimizes the power budget. We also show that DPDP outperforms existing heterogeneous scheduling policies that use performance metrics to decide how best to schedule applications on the big core.

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Section: Power and Thermal Managementmentioning

confidence: 99%

Maximizing Heterogeneous Processor Performance Under Power Constraints

Adileh

Eyerman²,

Jaleel

et al. 2016

ACM Trans. Archit. Code Optim.

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“…Placing PCM directly in contact with a the heat spreader of a single processor is beneficial for computational sprinting and other short-term cooling applications [29][30][31]38], but we require a much greater quantity of PCM in a datacentersized cooling system with a 24 hour thermal cycle [13,22]. Placing PCM in the server downwind of the processor sockets enables more PCM and still leverages the large temperature difference between idle and loaded levels.…”

Section: Integrating Pcm In Wscsmentioning

confidence: 99%

“…The thermal energy storage potential of paraffin has previously been examined on a small, single-chip scale for computational sprinting in [29][30][31] with promising results. While that work uses PCM in small quantities to reshape the load without impacting thermals, we take the opposite approach, using PCM to reshape the thermal profile with minimal change to the load.…”

Section: Related Workmentioning

confidence: 99%

Thermal time shifting

SkachMatt

AroraManish

HsuChang-Hong

et al. 2015

SIGARCH Comput. Archit. News

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Datacenters, or warehouse scale computers, are rapidly increasing in size and power consumption. However, this growth comes at the cost of an increasing thermal load that must be removed to prevent overheating and server failure. In this paper, we propose to use phase changing materials (PCM) to shape the thermal load of a datacenter, absorbing and releasing heat when it is advantageous to do so. We present and validate a methodology to study the impact of PCM on a datacenter, and evaluate two important opportunities for cost savings. We find that in a datacenter with full cooling system subscription, PCM can reduce the necessary cooling system size by up to 12% without impacting peak throughput, or increase the number of servers by up to 14.6% without increasing the cooling load. In a thermally constrained setting, PCM can increase peak throughput up to 69% while delaying the onset of thermal limits by over 3 hours.

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“…One example that has attracted a great deal of attention recently suggests the use of PCMs to store excessive heat generated during intense computation from mobile devices (e.g., cellular phones, tablets), which briefly ($1 s) exceeds the maximum steady-state power dissipation by an order of magnitude. Known as computational sprinting [11][12][13][14], this approach aims to improve responsiveness for bursty computational demands in devices restricted by passive cooling.…”

Section: Introductionmentioning

confidence: 99%

Figure-of-merit for phase-change materials used in thermal management

Shao

Raghavan

Kim

et al. 2016

International Journal of Heat and Mass Transfer

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a b s t r a c tIn this work, we utilize a figure-of-merit (FOM) to compare the performance of various phase-change materials (PCMs) in managing short bursts of high-power heat flux, particularly those associated with microprocessors undergoing bursty operation on a time scale of approximately one second. We numerically investigate the FOM for applications that have realistic boundary conditions and lack analytical solutions. We also fabricate microprocessor proxies with integrated PCM compartments mounted in a smartphone package, and experimentally demonstrate the use of a high-FOM PCM to buffer short heat spikes as large as 11 W/cm 2 .

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Utilizing Dark Silicon to Save Energy with Computational Sprinting

Cited by 32 publications

References 9 publications

Maximizing Heterogeneous Processor Performance Under Power Constraints

Maximizing Heterogeneous Processor Performance Under Power Constraints

Thermal time shifting

Figure-of-merit for phase-change materials used in thermal management

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