Van der waals BP/InSe heterojunction for tunneling field-effect transistors

Li, Hong; Wang, Qida; Xu, Peipei; Lü, Jing

doi:10.1007/s10853-021-05784-7

“…However, conventional TFETs have one main bottleneck, i.e., small on-state current (Ion), so that to obtain a highenough Ion is a major challenge for TFET application. To use a two-dimensional (2D) channel instead of a three-dimensional one is a valid scheme to promote the Ion of a TFET [5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23] mainly due to the enhanced electrostatic control by the atomic-thin body and the reduced scattering by the free-of-dangling-bond surface. To further introduce a homojunction or heterojunction architecture [15][16][17][18][19][20][21] in a TFET is a convincing scheme to continuously promote the Ion compared to a homogenous 2D channel.…”

Section: Introductionmentioning

confidence: 99%

“…To use a two-dimensional (2D) channel instead of a three-dimensional one is a valid scheme to promote the Ion of a TFET [5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23] mainly due to the enhanced electrostatic control by the atomic-thin body and the reduced scattering by the free-of-dangling-bond surface. To further introduce a homojunction or heterojunction architecture [15][16][17][18][19][20][21] in a TFET is a convincing scheme to continuously promote the Ion compared to a homogenous 2D channel. Experientially, 2D TFETs have been fabricated based on transition metal chalcogenides (TMD) and black phosphorene (BP) with good Ion and SS [24][25][26][27][28][29][30][31].…”

Section: Introductionmentioning

confidence: 99%

Device simulation of GeSe homojunction and vdW GeSe/GeTe heterojunction TFETs for high-performance application

Wang

¹

,

Xu

²

,

Li

³

et al. 2022

Self Cite

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Compared with a 2D homogeneous channel, the introduction of a 2D/2D homojunction or heterojunction is a promising method to promote the performance of a TFET mainly by controlling the tunneling barrier. We simulate the 10-nm-Lg double-gated GeSe homojunction TFETs and vdW GeSe/GeTe heterojunction TFETs using the ab initio quantum transport calculations. Two constructions are considered for both the homojunction and heterojunction TFETs by placing the BL GeSe and vdW GeSe/GeTe heterojunction as the source or drain while the channel and the remaining drain or source use ML GeSe. The on-state current (Ion) of the optimal n-type BL-ML GeSe source homojunction TFET and the optimal p-type vdW GeSe/GeTe drain heterojunction TFET are 2320 and 2387 μA μm -1 , respectively, which are 50% and 64% larger than Ion of the ML GeSe homogeneous TFET. Inspiringly, the device performances (Ion, intrinsic delay time τ, and power delay product PDP) of both the optimal ntype GeSe homojunction and p-type vdW GeSe/GeTe heterojunction TFETs meet the requirement of the International Roadmap for Device and Systems high-performance device for the year of 2034 (2020 version).

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“…At present, despite intensive research into 2D-heterostructure-based TFETs, 126 most experimental results do not meet theoretical expectations that deliver a high on-current and a very low SS value. 127,128 One main reason for this is interface problems like defects, oxides, and contaminates. 129,130 Therefore, improving the interface quality for obtaining the BTBT dominant current is critical for the future development of 2D TFETs.…”

Section: Transistor Modementioning

confidence: 99%

Emerging reconfigurable electronic devices based on two‐dimensional materials: A review

Fei

¹

,

Trommer

²

,

Mikolajick

³

et al. 2022

InfoMat

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As the dimensions of the transistor, the key element of silicon technology, are approaching their physical limits, developing semiconductor technology with novel concepts and materials has been the main focus of scientific research and industry. In recent years, emerging reconfigurable technologies that offer device-level run-time reconfigurability have been explored and shown the potential to enhance device and circuit functions. Two-dimensional (2D) materials possess exquisite electronic properties and provide a suitable platform for reconfigurable technology owing to their atomic-thin thickness and high sensitivity to external electrical fields. In this review, we present an intensive survey of 2D-material-based devices with diverse reconfigurability, including carrier polarity, threshold voltage control, as well as multifunctional configurations enabled by 2D heterostructures. We discuss the working principles for these devices in detail and highlight the important figures of merit for performance improvement. We further provide a forward-looking perspective on the opportunities and challenges of these reconfigurable devices based on 2D materials in the field of computing technologies.

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“…To use a two-dimensional (2D) channel instead of a three-dimensional one is a valid scheme to promote the Ion of a TFET [5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23] mainly due to the enhanced electrostatic control by the atomic-thin body and the reduced scattering by the free-of-dangling-bond surface. To further introduce a homojunction or heterojunction architecture [15][16][17][18][19][20][21] in a TFET is a convincing scheme to continuously promote the Ion compared to a homogenous 2D channel. Experientially, 2D TFETs have been fabricated based on transition metal chalcogenides (TMD) and black phosphorene (BP) with good Ion and SS [24][25][26][27][28][29][30][31].…”

Section: Introductionmentioning

confidence: 99%

“…However, conventional TFETs have one main bottleneck, i.e., small on-state current (Ion), so that to obtain a highenough Ion is a major challenge for TFET application. To use a two-dimensional (2D) channel instead of a three-dimensional one is a valid scheme to promote the Ion of a TFET [5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23] mainly due to the enhanced electrostatic control by the atomic-thin body and the reduced scattering by the free-of-dangling-bond surface. To further introduce a homojunction or heterojunction architecture [15][16][17][18][19][20][21] in a TFET is a convincing scheme to continuously promote the Ion compared to a homogenous 2D channel.…”

Section: Introductionmentioning

confidence: 99%

Device Simulation of The GeSe Homojunction And vdW GeSe/GeTe Heterojunction TFETs For High-Performance Application

Wang

¹

,

Xu

²

,

Li

³

et al. 2021

Preprint

Self Cite

View full text Add to dashboard Cite

Compared with a 2D homogeneous channel, the introduction of a 2D/2D homojunction or heterojunction is a promising method to promote the performance of a TFET mainly by controlling the tunneling barrier. We simulate the 10-nm-Lg double-gated GeSe homojunction TFETs and vdW GeSe/GeTe heterojunction TFETs using the ab initio quantum transport calculations. Two constructions are considered for both the homojunction and heterojunction TFETs by placing the BL GeSe and vdW GeSe/GeTe heterojunction as the source or drain while the channel and the remaining drain or source use ML GeSe. The on-state current (Ion) of the optimal n-type BL-ML GeSe source homojunction TFET and the optimal p-type vdW GeSe/GeTe drain heterojunction TFET are 2320 and 2387 μA μm-1, respectively, which are 50% and 64% larger than Ion of the ML GeSe homogeneous TFET. Inspiringly, the device performances (Ion, intrinsic delay time τ, and power delay product PDP) of both the optimal n-type GeSe homojunction and p-type vdW GeSe/GeTe heterojunction TFETs meet the requirement of the International Roadmap for Device and Systems high-performance device for the year of 2034 (2020 version).

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Van der waals BP/InSe heterojunction for tunneling field-effect transistors

Cited by 15 publications

References 56 publications

Device simulation of GeSe homojunction and vdW GeSe/GeTe heterojunction TFETs for high-performance application

Device simulation of GeSe homojunction and vdW GeSe/GeTe heterojunction TFETs for high-performance application

Emerging reconfigurable electronic devices based on two‐dimensional materials: A review

Device Simulation of The GeSe Homojunction And vdW GeSe/GeTe Heterojunction TFETs For High-Performance Application

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