Variability Analysis of 6t and 7t Sram Cell in Sub-45nm Technology

Islam, Aminul; Hasan, Mohd.

doi:10.31436/iiumej.v12i1.25

Cited by 20 publications

(3 citation statements)

References 20 publications

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“…[13], leakage and delay is graphically calculated from waveforms of simulated results as explained in [13][25] and [26] respectively. W/L ratio is taken as discussed in [27] and used 45nm PTM model [28] in this work of investigation.…”

Section: Memristor Characteristics Physics and Parametersmentioning

confidence: 99%

International Journal of Electronics and Telecommunications

Mustaqueem,

Ansari

2022

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This work aims to improve the total power dissipation, leakage currents and stability without disturbing the logic state of SRAM cell with concept called sub-threshold operation. Though, sub-threshold SRAM proves to be advantageous but fails with basic 6T SRAM cell during readability and writability. In this paper we have investigated a non-volatile 6T2M (6 Transistors & 2 Memristors) sub-threshold SRAM cell working at lower supply voltage of VDD=0.3V, where Memristor is used to store the information even at power failures and restores previous data with successful read and write operation overcomes the challenge faced. This paper also proposes a new configuration of non-volatile 6T2M (6 Transistors & 2 Memristors) subthreshold SRAM cell resulting in improved behaviour in terms of power, stability and leakage current where read and write power has improved by 40% and 90% respectively when compared to 6T2M (conventional) SRAM cell. The proposed 6T2M SRAM cell offers good stability of RSNM=65mV and WSNM=93mV which is much improved at low voltage when compared to conventional basic 6T SRAM cell, and improved leakage current of 4.92nA is achieved as compared.

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Section: Memristor Characteristics Physics and Parametersmentioning

confidence: 99%

International Journal of Electronics and Telecommunications

Mustaqueem,

Ansari

2022

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“…Among all the conventional memories, static random access memory (SRAM) is the most efficient memory because it does not need to be refreshed at regular intervals unlike dynamic random access memory [3]. However, they have higher area requirements because of the use of a higher number of metal−oxide −semiconductor field-effect transistors (MOSFETs) per cell.…”

Section: Introductionmentioning

confidence: 99%

Design and development of memristor‐based RRAM

Pal

Gupta

et al. 2019

IET Circuits, Devices & Systems

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A power-and variability-aware non-volatile resistive random access memory (RRAM) cell is presented. Non-volatility is achieved due to the use of a memristor as a memory element, which when integrated with a carbon nanotube field-effect transistor (CNFET) helps achieve tremendous robustness against process variation. The half-select issue, inherent in the 2T2M RRAM cell (state-of-the-art design based on the memristor) have been resolved and its circuit parameters have been compared with those of the proposed cell. Also, the proposed cell has been compared with the standard 6T SRAM (S6T) cell. The proposed cell shows 1.6×/4.08× narrower read delay/write delay variability compared with 2T2M. 5CNFET2M also shows 1.8× narrower read delay variability than that of S6T. Furthermore, the proposed cell shows 6.9× shorter write delay in comparison with the 2T2M RRAM cell. 5CNFET2M consumes 10 6 ×/1.34× lower power during hold mode compared with the conventional 6T static random access memory/2T2M RRAM cell. Furthermore, the proposed cell also shows improvement in hold power variability compared with both the cells. All the simulated data, presented here are at the nominal supply voltage of 1 V. These improvements are gained at the expense of slightly longer read time compared with 2T2M/S6T and 31.3× longer write delay compared with S6T.

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“…2) The voltage of N1 is change from 0 V to VDD while measuring voltage of QB.3) The voltage of N2 is changes from 0 V to VDD while measuring voltage of Q in the same path. 4) Now calculated voltages are plotting to obtain a butterfly curve[12]. Test setup for measuring SNM Above shown schematic shows a trial setup for measuring SNM.…”

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confidence: 99%

Design and Analysis of Magnetic Tunnel Junction Based Random Access Memory Cell

2020

American Journal of Electronics &Amp; Communication

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In this report, we presented an NV Random Access Memory cell using a novel easy and proficient model of Spin Transfer Torque Magnetic Tunnel Junction (STT-MTJ). Magnetic tunnel junction (MTJ) devices are CMOS well suited with high steadiness, high dependability and nonvolatility. The combination of magnetic tunnel junction with CMOS circuits in magnetic RAM (MRAM) or Magnetic FPGA can get the digital circuits to major advantages related with non-volatile facility like immediate on/off, Zero standby power use of goods and services. MTJ (Magnetic Tunnel Junction) devices have various advantages over other magneto-resistive devices for use in MRAM cells, like MRAM produces a big signal for the read operation and a varying resistance that can make the circuit. Due to these attributes, MTJ-MRAM can operate at high velocity. A completed simulation model for the 5T and 2MTJ SRAM design is shown in this report, which is grounded on the recently confirmed STT (Spin-Transfer Torque) writing technique which promises to take down the switching current losing to ~150µA and the STT RAM cache reduces total power consumption from 44.6µW-13.2µW. This model has been confirmed in Verilog A language and the whole work carried out and ran out on cadence virtuoso platform at 45nm.

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Variability Analysis of 6t and 7t Sram Cell in Sub-45nm Technology

Cited by 20 publications

References 20 publications

International Journal of Electronics and Telecommunications

International Journal of Electronics and Telecommunications

Design and development of memristor‐based RRAM

Design and Analysis of Magnetic Tunnel Junction Based Random Access Memory Cell

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