Variability driven gate sizing for binning yield optimization

Abstract

ISR develops, applies and teaches advanced methodologies of design and analysis toAbstract-Process variations result in a considerable spread in the frequency of the fabricated chips. In high performance applications, those chips that fail to meet the nominal frequency after fabrication are either discarded or sold at a loss which is typically proportional to the degree of timing violation. The latter is called binning. In this paper we present a gate sizing-based algorithm that optimally minimizes the binning yield-loss. Specifically we make the following contributions: 1) prove the binning yield function to be convex, 2) the proof does not make any assumptions about the sources of variability, their distributions (Gaussian/Non-Gaussian) or correlation, 3) by using Kelley's cutting-plane method for convex programs, we integrate our strategy with statistical timing analysis tools (STA), without making any assumptions about how STA is done, 4) if the objective is to optimize the traditional yield (and not binning yield) our approach can still optimize the same to a very large extent. Comparison of our approach with sensitivity-based approaches under fabrication variability shows an improvement of on average 72% in the binning yield-loss with an area overhead of an average 6%, while achieving a 2.69 times speedup under a stringent timing constraint. Moreover we show that a worstcase deterministic approach fails to generate a solution for certain delay constraints. We also show that optimizing the binning yield-loss minimizes the traditional yield-loss (although it is not a direct objective) with a 61% improvement from a sensitivity-based approach.

Evaluating Statistical Power Optimization

“…There are many papers that explore the benefits of adding statistical delay data into the optimization process [4], [5]- [10], and there are also a number of papers that use a statistical power measure [7], [11]- [15]. However, to the best of our knowledge, there is no publication that shows the benefits of using the statistical power measure alone.…”

Variability and Statistical Design

“…Approaches for optimizing the statistical power of the circuit, subject to timing yield constraints, can be presented as a convex formulation, as a second-order conic program 52) . For the binning model, a yield optimization problem is formulated 25) , providing a binning yield loss function that has a linear penalty for delay of the circuit exceeding the target delay; the formulation is shown to be convex.…”

Stochastic Optimization Over Correlated Data Set: A Case Study on VLSI Decoupling Capacitance Budgeting

“…The continuous semiconductor technology scaling leads to growing process variations (Agarwal & Nassif, 2007), and statistical optimization has been actively researched to cope with process variations. Recent examples include stochastic gate sizing for power reduction (Bhardwaj & Vrudhula, 2005;Mani et al, 2005) and for yield optimization (Davoodi & Srivastava, 2006;Sinha et al, 2005), stochastic buffer insertion to minimize clock delay , and adaptive body biasing with post-silicon tuning (Mani et al, 2006). However, all these papers ignore operation variation such as crosstalk difference over input vectors, power supply noise fluctuation over time, and processor temperature variation over workload.…”