Variable input delay CMOS logic for low power design

Abstract

Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after one or more inputs have changed is called the delay of the gate. A conventional CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. We propose a new gate design that has different delays along various input to output paths within the gate. This is accomplished by inserting selectively sized "permanently on" series transistors at the inputs of the logic gate. We demonstrate the use of the variable input delay CMOS gates for a totally glitch-free minimum dynamic power implementation of a digital circuit. Applying a previously described linear programming method to the c7552 benchmark circuit, we obtained a power saving of 58% over an unoptimized design. This power consumption was 18% lower than that for an alternative low power design using conventional CMOS gates. All circuits had the same overall delay. Since the overall delay was not allowed to increase, the glitch elimination with conventional gates required insertion of delay buffers on non-critical paths. The use of the variable input delay gates drastically reduced the required number of delay buffers.

Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation

“…hazard filtering [5,[8][9][10][11][12] and path balancing [6,8,11], referred to in this paper as glitch elimination. Compared to leakage power, dynamic power is normally much less sensitive to the process variation because of its approximately linear dependency on the process parameters.…”

IGS: The Novel Fast IC Power Ground Network Optimization Flow Based on Improved Gauss-Seidel Method

“…However, the size of TSVs is constant in the 28nm technologies. The optimization method presented in [12] inserts compensation cells when the delay of critical path exceeds the allowed value to reduce IR-drop. All the researches mentioned above reduce IR-drop and optimize the PGN of chips finally.…”

Input-specific dynamic power optimization for VLSI circuits

“…For a circuit where the total propagation delay is restricted, the conventional LP solution requires the insertion of many delay elements in non-critical paths. To reduce the additional power consumed by these elements, Raja et al [9,10,11] have proposed new type of gates with different IO delays incorporating transmission-gates. Uppalapati et al [13] used customized resistive feedthrough cells as delay elements, which consumed negligible amount of switching power.…”

“…Uppalapati et al [13] used customized resistive feedthrough cells as delay elements, which consumed negligible amount of switching power. Howsoever small in number, delay elements [10,13] add some capacitive loading that increases the per-transition dynamic power. Besides, they increase the total circuit area.…”