Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design

Verma, Subhash; Brisk, Philip; Ienne,

doi:10.1109/date.2008.4484850

Cited by 137 publications

(169 citation statements)

References 11 publications

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“…To correct the error, '1' should be added to the approximate (inaccurate) output, and the error correction can be implemented with an incrementor circuit. With these simple error detection and correction circuits, our proposed adder can be implemented to have variable latency like the previous VLSA adder [12], with a small overhead for an error detection and correction (EDC) system. Figure 4 shows an EDC system with our proposed adder.…”

Section: Error Detection and Correction For Accurate Computationmentioning

confidence: 99%

“…However, accurate computations are still required at certain times, according to the application. VLSA [12] can provide accurate results, but has large delay and area overhead for the error detection and correction. The central contribution of our present work is to propose an approximate adder which supports both accurate and inaccurate computation with error-correction and accuracy-configuration capability.…”

Section: Introductionmentioning

confidence: 99%

“…Lu [7] introduces a faster adder which has shorter carry chains and considers only the previous k bits of input in computing a carry bit. Verma et al [12] provide a variable latency speculative adder (V LSA), which is a reliable version of the Lu adder [7] with error detection and correction. Shin et al [10] also propose a data path redesign technique for various adders which cuts the critical path in the carry chain.…”

Section: Introductionmentioning

confidence: 99%

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Accuracy-configurable adder for approximate arithmetic designs

Kahng

Kang

2012

Proceedings of the 49th Annual Design Automation Conference

381

187

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Approximation can increase performance or reduce power consumption with a simplified or inaccurate circuit in application contexts where strict requirements are relaxed. For applications related to human senses, approximate arithmetic can be used to generate sufficient results rather than absolutely accurate results. Approximate design exploits a tradeoff of accuracy in computation versus performance and power. However, required accuracy varies according to applications, and 100% accurate results are still required in some situations. In this paper, we propose an accuracy-configurable approximate (ACA) adder for which the accuracy of results is configurable during runtime. Because of its configurability, the ACA adder can adaptively operate in both approximate (inaccurate) mode and accurate mode. The proposed adder can achieve significant throughput improvement and total power reduction over conventional adder designs. It can be used in accuracy-configurable applications, and improves the achievable tradeoff between performance/power and quality. The ACA adder achieves approximately 30% power reduction versus the conventional pipelined adder at the relaxed accuracy requirement.

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Section: Error Detection and Correction For Accurate Computationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Accuracy-configurable adder for approximate arithmetic designs

Kahng

Kang

2012

Proceedings of the 49th Annual Design Automation Conference

381

187

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show abstract

“…By using error compensation approaches, the error can be reduced compared to simply breaking the carry chain. ETAIIM [29], ACA-SD [12], Lu's adder [19], and ACA-X [26] use a carry-lookahead (CLA)-based approach to shorten the longest carry propagation path in the adder. These adders are composed of CLA submodules, and the numbers and sizes of the submodules can be configured at design time.…”

Section: B Approximate Arithmetic Modulesmentioning

confidence: 99%

Statistical analysis and modeling for error composition in approximate computation circuits

Chan

Kahng

Kang

et al. 2013

2013 IEEE 31st International Conference on Computer Design (ICCD)

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Abstract-Aggressive requirements for low power and high performance in VLSI designs have led to increased interest in approximate computation. Approximate hardware modules can achieve improved energy efficiency compared to accurate hardware modules. While a number of previous works have proposed hardware modules for approximate arithmetic, these works focus on solitary approximate arithmetic operations. To utilize the benefit of approximate hardware modules, CAD tools should be able to quickly and accurately estimate the output quality of composed approximate designs. A previous work [10] proposes an interval-based approach for evaluating the output quality of certain approximate arithmetic designs. However, their approach uses sampled error distributions to store the characterization data of hardware, and its accuracy is limited by the number of intervals used during characterization.In this work, we propose an approach for output quality estimation of approximate designs that is based on a lookup table technique that characterizes the statistical properties of approximate hardwares and a regression-based technique for composing statistics to formulate output quality. These two techniques improve the speed and accuracy for several error metrics over a set of multiply-accumulator testcases. Compared to the interval-based modeling approach of [10], our approach for estimating output quality of approximate designs is 3.75× more accurate for comparable runtime on the testcases and achieves 8.4× runtime reduction for the error composition flow. We also demonstrate that our approach is applicable to general testcases.

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“…All these techniques are based on the central concept of VOS, coupled with additional circuitry for correcting or limiting the resulting errors. In [11], a fast but "inaccurate" adder is proposed. It is based on the idea that on average, the length of the longest sequence of propagate signals is approximately log n, where n is the bitwidth of the two integers to be added.…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of Booth Multiplier using Approximate Adders

Keskar¹,

Mote²

2015

International Journal of Innovative Research in Electrical, Ele

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Low power is an imperative requirement for portable multimedia devices employing various signal processing algorithms and architectures. In most multimedia applications, human beings can gather useful information from slightly erroneous outputs. Therefore, we do not need to produce exactly correct numerical outputs. Previous research in this context exploits error resiliency primarily through voltage overscaling, utilizing algorithmic and architectural techniques to mitigate the resulting errors. In this paper, we propose logic complexity reduction at the transistor level as an alternative approach to take advantage of the relaxation of numerical accuracy. We demonstrate this concept by proposing various imprecise or approximate full adder cells with reduced complexity at the transistor level, and utilize them to design approximate multi-bit adders. In addition to the inherent reduction in switched capacitance, our techniques result in significantly shorter critical paths, enabling voltage scaling.

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Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design

Abstract: Abstract

Cited by 137 publications

References 11 publications

Accuracy-configurable adder for approximate arithmetic designs

Accuracy-configurable adder for approximate arithmetic designs

Statistical analysis and modeling for error composition in approximate computation circuits

Design and Implementation of Booth Multiplier using Approximate Adders

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