Variable length mixed radix MDC FFT/IFFT processor for MIMO‐OFDM application

Abstract

This study presents a variable length multi-path delay commutator fast Fourier transform (FFT)/inverse FFT (IFFT) architecture for a multiple input multiple output orthogonal frequency division multiplexing system. It supports the FFT/ IFFT lengths of 512/256/128/64 samples to process each symbol carried by eight spatial streams and achieves a speed of 160 MHz to meet the IEEE 802.11ac timing requirements. A resource scheduling methodology to minimise the hardware complexity of the design is proposed and adopted in the architecture presented. A novel stagger word length strategy is also proposed and applied to achieve the better accuracy with lesser hardware. Here, the signal to quantisation noise ratio of 57.23 dB is obtained. The twiddle coefficient storage space is significantly compressed to achieve the coefficient generation with reduced hardware. The design is implemented using the TSMC-65 nm complementary metal oxide semiconductor technology with a supply voltage of 1 V at 160 MHz. The implementation results show that the architecture has a gate count of 3,48,013 with power consumption of 105.1 mW and area of 0.492 mm 2. The hardware complexity and performance of the design are compared with earlier reported architectures. It is observed that the proposed design achieves better performance in terms of hardware complexity and normalised energy for the given specifications.

Area-Efficient FFT Kernel with Improved Use of GI for Multistandard MIMO-OFDM Applications

“…By effectively using the parallel data paths and operation units, the multipath processing feature of MDC can be applied to the FFT computation of multiple streams [20]. Therefore, several FFT designs based on MDC structures have been presented for MIMO-OFDM applications [20][21][22][23]. Figure 3 shows the block diagram for the conventional M-path MDC architecture applied to MIMO-OFDM FFT of M streams, where the feedforward multipath data is processed using switch blocks, FIFOs, butterfly units and multipliers.…”

“…Furthermore, some previous studies [21,25,28] discuss the schemes of hardware cost reduction for multipliers located at multiple paths (Figures 3 and 4). In general, these MDC or MDF approaches [20][21][22][23][24][25][26][27][28][29] enable multipath/parallel operations associated with multiple FFT streams (i.e., the number of data paths and FFT streams is equal).…”

“…Most MIMO-OFDM standards have variable FFT lengths and stream levels, and thus, the corresponding MDC or MDF FFT designs generally employ a reconfigurable structure to support various FFT operation modes specified at the aimed specification [7,20,22]. In addition, considerable research has been conducted on advanced restructure schemes for multimode FFT processors that support multiple MIMO-OFDM standards [28,29].…”

“…However, among the mainstream MIMO-OFDM standards (WiFi, LTE, and 5G applications), 1-to 4-stream 128/64-point FFT is implemented with a base operation mode [20][21][22][23][25][26][27][28]. This is one approach, using which a common optimized four-stream 128/64-point FFT kernel can be developed as a base module to construct specified M-stream N-point FFT/IFFT processors.…”

Energy efficient VLSI architecture of real‐valued serial pipelined FFT

“…This reduces the area‐complexity of FFT architecture, but successive use of memory banks and processing elements lead to higher power consumption. On the other hand, pipelined FFT architectures [9–12] have the advantage of lower power with higher throughput over the memory‐based FFT architectures [13–17]. They are further categorised on the basis of samples processed per iteration, namely, serial (or single‐path) and parallel (or multi‐path) architectures.…”