Variable ordering for taylor expansion diagrams

Gomez-Prado, D.; Ren, Qinyuan; Askar, Serkan; Ciesielski, Maciej; Boutillon, Emmanuel

doi:10.1109/hldvt.2004.1431235

Cited by 11 publications

(5 citation statements)

References 5 publications

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“…Therefore, it is desirable to search for a variable order that would minimize the size of a TED. We have recently developed a dynamic variable ordering for TEDs based on local swapping of adjacent variables in the diagram, similar to those employed in BDD ordering [57], [58]. It has been shown that, similarly to BDDs, local swapping of adjacent variables does not affect the structure of the diagram outside of the swapping area.…”

Section: Implementation and Experimental Resultsmentioning

confidence: 99%

Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs

Ciesielski

Kalla

Askar

2006

IEEE Trans. Comput.

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Abstract-A Taylor Expansion Diagram (TED) is a compact, word-level, canonical representation for data flow computations that can be expressed as multivariate polynomials. TEDs are based on a decomposition scheme using Taylor series expansion that allows one to model word-level signals as algebraic symbols. This power of abstraction, combined with the canonicity and compactness of TED, makes it applicable to equivalence verification of dataflow designs. The paper describes the theory of TEDs and proves their canonicity. It shows how to construct a TED from an HDL design specification and discusses the application of TEDs in proving the equivalence of such designs. Experiments were performed with a variety of designs to observe the potential and limitations of TEDs for dataflow design verification. Application of TEDs to algorithmic and behavioral verification is demonstrated. Index Terms-Register transfer level-design aids, verification; arithmetic and logic structures-verification; symbolic and algebraic manipulation.

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Section: Implementation and Experimental Resultsmentioning

confidence: 99%

Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs

Ciesielski

Kalla

Askar

2006

IEEE Trans. Comput.

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“…From equation (9), it can be observed that variable ordering as discussed in [8] cannot be done across the register boundary. That is, two adjecent variables x n and y 1 connected through a retimed edge cannot be swapped, because moving the partial derivatives inside or outside the operator () nR requires a retiming operation first.…”

Section: Implications Of Retiming On Variable Ordering Theorem 33 a mentioning

confidence: 98%

Retiming arithmetic datapaths using Timed Taylor Expansion Diagrams

Gomez-Prado

Kim

Ciesielski

et al. 2010

2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)

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This paper describes an extension to the Taylor Expansion Diagrams (TED), called Timed TEDs, which makes it possible to represent sequential arithmetic datapaths. Timed TEDs enable register and clock period minimization while performing factorizations and common sub expression eliminations in the data flow graph (DFG). Specifically, timed TEDs allow a wider range of retiming options as the computations in the DFG can be modified while performing retiming. In this paper we discuss the formalism of timed TEDs and the restrictions it imposes on the TED variable ordering.

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“…TED is a graph-based representation for multi-variate polynomials [2,13] obtained from Taylor expansion:…”

Section: Polynomial Representation Using Tedmentioning

confidence: 99%