Variation-Aware Design of Custom Integrated Circuits: A Hands-on Field Guide

McConaghy, Trent; Breen, Kristopher; Dyck, Jeffrey S.; Gupta, Amit Kumar

doi:10.1007/978-1-4614-2269-3

Cited by 72 publications

(41 citation statements)

References 46 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The above methodology has no interdevice dependencies and can be generalized to a larger device inventory [28]. This data parallelism is highly compatible with the multi-/many-core paradigm [29] observed in the computing infrastructure of modern design houses [30].…”

Section: Simulation Methodology and Test Case For A Single Devicementioning

confidence: 96%

“…We estimate the functional yield of the target circuit, namely the percentage of samples that exhibit correct functionality. Derivation of such metrics is of major importance at design time and many methodologies exist solving this problem [30]. Given the inherent time-and workload-dependency of the proposed model, we can estimate the functional yield at different instances of circuit lifetime.…”

Section: Design Flow Compatibilitymentioning

confidence: 99%

“…Based on the model's workload dependency, we test dynamic alterations to the circuits workload and observe their impact on the functional yield. Such capabilities are very important for the design of reliable ICs, especially at aggressively downscaled technologies [30].…”

Section: Design Flow Compatibilitymentioning

confidence: 99%

See 2 more Smart Citations

Atomistic Pseudo-Transient BTI Simulation With Inherent Workload Memory

Rodopoulos

Weckx

Noltsis

et al. 2014

IEEE Trans. Device Mater. Relib.

View full text Add to dashboard Cite

Bias Temperature Instability (BTI) is a major concern for the reliability of decameter to nanometer devices. Older modeling approaches fail to capture time-dependent device variability or maintain a crude view of the device's stress. Previously, a two-state atomistic model has been introduced, which is based on gate stack defect kinetics. Its complexity has been preventing seamless integration in simulations of large device inventories over typical system lifetimes. In this paper, we present an approach that alleviates this complexity. We introduce a novel signal representation for the gate stress. Using this format, atomistic BTI simulations require less model iterations while exhibiting minimum accuracy degradation. We also enable full temperature and voltage supply dependency since these attributes are far from constant in modern integrated systems. The proposed simulation methodology retains both the atomistic property and the workload memory that remain major differentiators of defect-based BTI simulation, in comparison to state-of-the-art approaches.

show abstract

Section: Simulation Methodology and Test Case For A Single Devicementioning

confidence: 96%

Section: Design Flow Compatibilitymentioning

confidence: 99%

See 1 more Smart Citation

Atomistic Pseudo-Transient BTI Simulation With Inherent Workload Memory

Rodopoulos

Weckx

Noltsis

et al. 2014

IEEE Trans. Device Mater. Relib.

View full text Add to dashboard Cite

show abstract

“…Process parameter variations define the maximum clock frequency and power consumption that the chip can operate [2,4]. Process variations and the continuous demand for more performance electronic devices and systems have put in struggled the semiconductor industry [5,6]. Device sizes have scaled-down in the order of few nanometers to fulfill the consumer demand.…”

Section: Introductionmentioning

confidence: 99%

“…The use of CAD tools to design optimization of the overall circuit delay has been proposed in the literature [7,8,9]. Most common methodologies used to design circuits tolerant to process variations are the gate-sizing optimization algorithms [7,8,9], custom design [5,10,11], parallel-gates [10,12] and specialized libraries [13].…”

Section: Introductionmentioning

confidence: 99%

Exploring a homotopy approach for the design of nanometer digital circuits tolerant to process variations

Rodríguez

Garcia-Gervacio

Leal

2018

IEICE Electron. Express

View full text Add to dashboard Cite

It is known that process parameter variation degrades the performance of nanometer integrated circuits. Process variations reduce the maximum clock frequency operation of the chips. Diverse strategies have been proposed in the literature to overcome this issue, especially optimization algorithms (gate-sizing algorithms). However, convergence related problems have limited their use. In this work, a homotopy approach for the design of nanometer digital circuits tolerant to process variations is proposed. Two optimization strategies are developed in this work, the first based on the homotopy continuation method (HCM) and the second based on a modification of HCM, called in this work reboot homotopy continuation method (RHCM). Three logic paths were implemented to validate the algorithms. The optimization results obtained with the proposed strategies are compared with a Lagrange-Multipliers-based framework. Results obtained from HCM method are equivalent to the obtained with Lagrange Multipliers. On the other side, results obtained from the RHCM method are more accurate than the obtained with HCM and Lagrange Multipliers. Furthermore, the area used to implement the logic paths is lower when RHCM is applied. Moreover, the number of Newton-Rhapson iterations required to find the solutions are lower when RHCM is used; consequently, time computing is also lower.

show abstract

Optimal transistor sizing for maximum yield in variation‐aware standard cell design

Abbas

Olivieri

2015

Circuit Theory & Apps

View full text Add to dashboard Cite

Process variability, in addition to wide temperature and supply voltage variation ranges, severely degrades the fabrication outcome (yield) of digital cells as for the fulfillment of performance specification bounds. This paper presents the application of mathematical optimization to the design of standard cells that are robust to process variations even in worst-case operating conditions. The method attains the optimal sizing of individual transistors in the cell for maximizing the statistical yield referring to leakage power and propagation delay bounds, with local and global process variations specified by industrial process development kits (PDKs). The approach is demonstrated for a 40 nm low-power standard threshold voltage Complementary Metal Oxide Semiconductor (CMOS) technology, for an intended operating temperature range [À40°C, 125°C] and supply voltage range [0.95 V, 1.05 V]. The reported optimization results show a yield improvement from an initial 50% to 99.9%, and Simulation Program with Integrated Circuit Emphasis (SPICE)-level Monte Carlo analysis confirmed the estimated yield of the obtained circuits.slow corners for such devices. However, digital corners account for global variation, not including local variations effects, which are critical in the present scenario [24]. Also, digital corners are not design-specific, which is necessary to determine the impact of variation. Such characteristics limit the accuracy of the digital corners and cannot be considered as accurate indicators of performance variation bounds [25]. In order to achieve effective variation-aware design, we must thoughtfully account both the statistical inter-die and intra-die variations, and the operating condition fluctuations.As a result, statistical optimization for yield has become a crucial task in IC design, and because the specifications of an IC usually have challenging trade-offs, requiring multidimensional, multiobjective optimization, the role of mathematical techniques for circuit analysis and yield optimization has become essential to obtain solutions that satisfy the requested performance in the least time effort [6][7][8][9]14]. Transistor level designs like standard cells are most susceptible to parametric yield issues caused by process/operating variations [10,11,13,16,17,23] and are the scope of this work. Several design time transistor sizing algorithms have been proposed in literature to optimize the delay and/or power variations. In [27], authors report an approach for the variation-tolerant gate sizing incorporating statistical timing model. The proposed approach formulates a statistical objective and timing constraints and solves the resulting nonlinear optimization. However, this seems computationally difficult and therefore does not fit to complex circuits. Other techniques proposed in [28][29][30]36] rely on the notion of capturing the delay distribution by performing the statistical static timing analysis instead of static timing analysis. Later, gate sizing is carried out using either nonlinear prog...

show abstract

Variation-Aware Design of Custom Integrated Circuits: A Hands-on Field Guide

Cited by 72 publications

References 46 publications

Atomistic Pseudo-Transient BTI Simulation With Inherent Workload Memory

Atomistic Pseudo-Transient BTI Simulation With Inherent Workload Memory

Exploring a homotopy approach for the design of nanometer digital circuits tolerant to process variations

Optimal transistor sizing for maximum yield in variation‐aware standard cell design

Contact Info

Product

Resources

About