Variation-aware routing for FPGAs

Abstract

Chip design in the nanometer regime is becoming increasingly difficult due to process variations. ASIC designers have adopted statistical optimization techniques to mitigate the effects of variations. The FPGA community on the other hand, has only recently started focussing on the effects of variations. This paper presents a comparative study of the impact of variations on designs mapped to FPGAs and ASICs to get a measure of the severity of the problem in both the FPGA and ASIC domains. We also propose a variation aware router that reduces the yield loss by 7.61X, or the circuit delay by 3.95% for the same yield for the MCNC benchmarks.

Statistical Generic and Chip-Specific Skew Assignment for Improving Timing Yield of FPGAs

“…In this work we use deterministic place and route algorithms since our objective is to study the effectiveness of the skew assignment technique. However, skew assignment can be used in conjunction with statistical place and route algorithms ( [1], [3]) to augment the timing yield further and to meet more aggressive timing specifications. Using SSTA, we set the values of T fast ,T medium and T slow such that fast, medium and slow bins contain 40%,30% and 29.9% of the chips respectively [1].…”

“…We use the spatial correlation model presented in [7]. Due to lack of real foundry data, we use the process parameters presented in [3]. The total 3σ variations in L ef f , W ef f , W int and T int are approximately 15%, 10%, 15% and 6% respectively.…”

“…To alleviate the problems due to variability, statistical optimization techniques have been adopted for a long time by ASIC designers. Recently the FPGA community has also started to take note of the potential pitfalls associated with not considering process variations in the design phase( [1], [2], [3]). Statistical static timing analysis has been widely used to account for variations and to produce tighter delay distributions to improve timing yield.…”

FPGA Architecture: Survey and Challenges

“…Proposals include introducing statistical static timing analysis (SSTA) to FPGA CAD tools to improve delays by avoiding the margins that are necessary for traditional static timing analysis [177,184], testing multiple logically equivalent configurations of the FPGA to find one that is functional at the desired speed [177], generating critical paths that will be more robust in the face of variation [147] or customizing the implementation on the FPGA for the variations of each specific device [57,111]. With the increased impact of variability that is expected in future process generations, it is likely a combination of architectural and circuit-level changes will be needed in conjunction with a number of CAD tool innovations.…”

Fine-grained characterization of process variation in FPGAs

“…Traditional approaches to handle process variations are to increase timing safety margins but doing this in a global manner is wasteful. The reconfigurability available in field programmable gate array (FPGA) devices offers the potential for designers to optimize circuit placement and routing at runtime [2] [3], and this feature may be extremely beneficial to tolerate severe process variation and enhance timing yield of FPGA design in the future.…”