Variation-aware static and dynamic writability analysis for voltage-scaled bit-interleaved 8-T SRAMs

Chandra,; Aitken,; Blaauw,; Sylvester,

doi:10.1109/islped.2011.5993627

Cited by 15 publications

(12 citation statements)

References 18 publications

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“…Disturbance errors are a general class of reliability problem that afflicts not only DRAM, but also other memory and storage technologies: SRAM [16,26,40], flash [10,12,13,19,25], and hard-disk [36,63,68]. Van de Goor and de Neef [64] present a collection of production tests that can be employed by DRAM manufacturers to screen faulty chips.…”

Section: Other Related Workmentioning

confidence: 99%

Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors

Kim¹,

Daly²,

Kim³

et al. 2014

2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)

454

1,019

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Abstract. Memory isolation is a key property of a reliable and secure computing system -an access to one memory address should not have unintended side effects on data stored in other addresses. However, as DRAM process technology scales down to smaller dimensions, it becomes more difficult to prevent DRAM cells from electrically interacting with each other. In this paper, we expose the vulnerability of commodity DRAM chips to disturbance errors. By reading from the same address in DRAM, we show that it is possible to corrupt data in nearby addresses. More specifically, activating the same row in DRAM corrupts data in nearby rows. We demonstrate this phenomenon on Intel and AMD systems using a malicious program that generates many DRAM accesses. We induce errors in most DRAM modules (110 out of 129) from three major DRAM manufacturers. From this we conclude that many deployed systems are likely to be at risk. We identify the root cause of disturbance errors as the repeated toggling of a DRAM row's wordline, which stresses inter-cell coupling effects that accelerate charge leakage from nearby rows. We provide an extensive characterization study of disturbance errors and their behavior using an FPGA-based testing platform. Among our key findings, we show that (i) it takes as few as 139K accesses to induce an error and (ii) up to one in every 1.7K cells is susceptible to errors. After examining various potential ways of addressing the problem, we propose a low-overhead solution to prevent the errors.

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Section: Other Related Workmentioning

confidence: 99%

Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors

Kim¹,

Daly²,

Kim³

et al. 2014

2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)

454

1,019

View full text Add to dashboard Cite

show abstract

“…Disturbance errors are a general class of reliability problems that is present in not only DRAM, but also other memory and storage technologies. All scaled memory technologies, including SRAM [62,93,121], flash [42, 45, 46, 50-53, 67, 167, 168, 171, 214], and hard disk drives [110,234,249], exhibit such disturbance problems. In fact, two of our works experimentally examine read disturb errors in flash memory: 1) our original work in DATE 2012 [42] that provides a rigorous experimental study of error patterns in modern MLC NAND flash memory chips demonstrates the importance of read disturb error patterns, 2) our recent work at DSN 2015 [51] experimentally characterizes the read disturb errors in flash memory, shows that the problem is widespread in recent flash memory chips, and develops mechanisms to correct such errors in the flash memory controller.…”

Section: H Rowhammer In a Broader Contextmentioning

confidence: 99%

RowHammer: A Retrospective

Mutlu

Kim

2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

163

129

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This retrospective paper describes the RowHammer problem in Dynamic Random Access Memory (DRAM), which was initially introduced by Kim et al. at the ISCA 2014 conference [133]. RowHammer is a prime (and perhaps the first) example of how a circuit-level failure mechanism can cause a practical and widespread system security vulnerability. It is the phenomenon that repeatedly accessing a row in a modern DRAM chip causes bit flips in physically-adjacent rows at consistently predictable bit locations. RowHammer is caused by a hardware failure mechanism called DRAM disturbance errors, which is a manifestation of circuit-level cell-to-cell interference in a scaled memory technology.Researchers from Google Project Zero demonstrated in 2015 that this hardware failure mechanism can be effectively exploited by user-level programs to gain kernel privileges on real systems. Many other follow-up works demonstrated other practical attacks exploiting RowHammer. In this article, we comprehensively survey the scientific literature on RowHammer-based attacks as well as mitigation techniques to prevent RowHammer. We also discuss what other related vulnerabilities may be lurking in DRAM and other types of memories, e.g., NAND flash memory or Phase Change Memory, that can potentially threaten the foundations of secure systems, as the memory technologies scale to higher densities. We conclude by describing and advocating a principled approach to memory reliability and security research that can enable us to better anticipate and prevent such vulnerabilities.

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“…Meanwhile, owing to the progress of the semiconductor techniques, the dimension of transistors as well as the supply voltage is scaling. Although supply voltage scaling has been proved to be the most effective method for energy saving [1,2,3,4,5,6], it will seriously deteriorate the read stability and write ability of the memory cell. Moreover, due to the process variations existing, the performance described above will be further deteriorated in low voltage, also in the future process nodes, which will result in the failure probability of read or write operations increasing [2,6,7,8,9,10].…”

Section: Introductionmentioning

confidence: 99%

“…Decoupling the storage nodes with bit-line or lowering the voltage drop between the driver and access transistors is the efficient way to enhance read stability [11]. And, cutting the feedback loop, boosting wordline (WL) voltage and decreasing the supply voltage of cross-couple inverters can increase write margins [1,3,4,13]. However, the previous techniques only improve one of the write margin and read stability, or the single-port, read/write, them generally degrade the speed of operation and makes the sense amplifier faced a challenge [1,3,6,12,13].…”

Section: Introductionmentioning

confidence: 99%

Read/write margin enhanced 10T SRAM for low voltage application

Peng

Guan

et al. 2016

IEICE Electron. Express

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Abstract:The static random access memory (SRAM) is indispensable for high performance applications. With technology scaling, the device size as well as the operation supply voltage (VDD) is reduced. However, with the supply voltage decreasing, the performance of the conventional 6T SRAM is deteriorated seriously. In this letter, a symmetrical 10T SRAM with dramatically improved read stability and write ability is proposed. The simulation results indicate that, compared with the conventional 6T SRAM, the read static noise margin (RSNM) and write margin (WM) of the proposed 10T SRAM achieve 2.43× and 4.51× improvement, respectively, at a 0.8 V supply voltage in SMIC 65 nm technology. As a result, lower failure probability in access operations is expected. Moreover, the minimum supply voltage (VDD min ) of the proposed 10T SRAM achieves ∼0.32× compared with that of conventional 6T cell. Additionally, it also shows a better tolerance to the varying process variations.

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Variation-aware static and dynamic writability analysis for voltage-scaled bit-interleaved 8-T SRAMs

Cited by 15 publications

References 18 publications

Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors

Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors

RowHammer: A Retrospective

Read/write margin enhanced 10T SRAM for low voltage application

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