Variation of Chemical Vapor Deposited SiO<sub>2</sub> Density Due to Generation and Shrinkage of Open Space During Thermal Annealing

Sometani, Mitsuru; Hasunuma, Ryu; Ogino, Michiko; Kuribayashi, Hitoshi; Sugahara, Yoshiyuki; Uedono, Akira; Yamabe, Kikuo

doi:10.1143/jjap.51.021101

Cited by 13 publications

(3 citation statements)

References 15 publications

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“…The smallest void that SAM can detect is 40 μm. Such size would be too big as open space to be detected by 23 have demonstrated that the S parameter of SiO 2 film deposited using tetraethoxysilane (TEOS) significantly increased after the annealing at 600 °C due to the desorption of impurities present in the open space. A similar mechanism could be envisioned for the bonded SiO 2 samples: open spaces detected by PAS are created during the annealing process by desorption of molecules such as water.…”

Section: Resultsmentioning

confidence: 99%

Origin of Voids at the SiO₂/SiO₂ and SiCN/SiCN Bonding Interface Using Positron Annihilation Spectroscopy and Electron Spin Resonance

Nagano¹,

Inoue²,

Phommahaxay³

et al. 2023

ECS J. Solid State Sci. Technol.

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To obtain reliable 3D stacking, a void-free bonding interface should be obtained during wafer-to-wafer direct bonding. Historically, SiO2 is the most studied dielectric layer for direct bonding applications, and it is reported to form voids at the interface. Recently, SiCN has raised as a new candidate for bonding layer. Further understanding of the mechanism behind void formation at the interface would allow to avoid bonding voids on different dielectrics. In this study, the void formation at the bonding interface was studied for a wafer pair of SiO2 and SiCN deposited by plasma enhanced chemical vapor deposition (PECVD). The presence of voids for SiO2 was confirmed after the post-bond anneal (PBA) at 350°C by Scanning Acoustic Microscopy. Alternatively, SiCN deposited by PECVD has demonstrated a void-free interface after post bond annealing. To better understand the mechanism of void formation at the SiO2 bonding interface, we used Positron Annihilation Spectroscopy (PAS) to inspect the atomic-level open spaces and Electron Spin Resonance (ESR) to evaluate the dangling bond formation by N2 plasma activation. By correlating these results with previous results, a model for void formation mechanism at the SiO2 and the absence of for SiCN bonding interface is proposed.

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Section: Resultsmentioning

confidence: 99%

Origin of Voids at the SiO₂/SiO₂ and SiCN/SiCN Bonding Interface Using Positron Annihilation Spectroscopy and Electron Spin Resonance

Nagano¹,

Inoue²,

Phommahaxay³

et al. 2023

ECS J. Solid State Sci. Technol.

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“…Sometani et al reported that evaporation of impurities such as C 2 H 4 , CO, and H 2 O from open spaces in TEOS-SiO 2 films increased the S value, which was attributed to the formation and annihilation of parapositronium in empty open spaces. A further increase in the S value was observed following annealing at 250–350 °C, and this temperature range agrees with that corresponding to the first desorption peak I shown in Figure .…”

Section: Resultsmentioning

confidence: 99%

Temporary Direct Bonding by Low Temperature Deposited SiO₂ for Chiplet Applications

Onishi,

Kitagawa,

Teranishi

et al. 2024

ACS Appl. Electron. Mater.

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Die-to-wafer hybrid bonding is a crucial technology in advanced chiplet integration systems. Temporary die bonding on wafers and subsequent debonding are key aspects of this process. However, conventional polymer-based temporary bonding techniques involve several challenges such as issues related to the accurate placement of the die. Although direct bonding is a promising technology, such processes normally involve permanent bonds. The present study demonstrates an innovative temporary bonding method based on plasmaactivated direct bonding and examines the associated bonding/debonding mechanisms. In this work, a dielectric bonding film was deposited at a relatively low temperature by chemical vapor deposition. This method offers several advantages, including high alignment accuracy, limited risk of die shift, and cost reduction based on removal of the carrier wafer grinding process. Wafer bonding was performed with SiO 2 films deposited at low temperatures, and voids were formed at the bonding interfaces during postbond annealing. The bonding energy was sufficiently low even after annealing to allow wafer pairs to be released as a consequence of voids serving as initiation points for debonding. Desorption gas analysis established that the SiO 2 films absorbed significant moisture from ambient air, which was the root cause of void formation. Die-to-wafer bonding tests confirmed the formation of voids at the bonding interfaces. This dielectric is likely to have applications as a temporary bonding material in chiplet integration systems.

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“…In fact, short timescale UV-LA may also address this problem. A chemically grown SiO 2 thin film is known to have a smaller density than thermally grown films, as well as some impurities remaining inside [22]. Such a situation would also be the case for a subnanometer-thick SiO 2 thin film grown by wet chemical cleaning for a CMOS gate stack.…”

Section: Reliability Annealing For High-k/sio 2 /Si Gate Stacksmentioning

confidence: 99%

Recent Progresses and Perspectives of UV Laser Annealing Technologies for Advanced CMOS Devices

et al. 2022

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The state-of-the-art CMOS technology has started to adopt three-dimensional (3D) integration approaches, enabling continuous chip density increment and performance improvement, while alleviating difficulties encountered in traditional planar scaling. This new device architecture, in addition to the efforts required for extracting the best material properties, imposes a challenge of reducing the thermal budget of processes to be applied everywhere in CMOS devices, so that conventional processes must be replaced without any compromise to device performance. Ultra-violet laser annealing (UV-LA) is then of prime importance to address such a requirement. First, the strongly limited absorption of UV light into materials allows surface-localized heat source generation. Second, the process timescale typically ranging from nanoseconds (ns) to microseconds (μs) efficiently restricts the heat diffusion in the vertical direction. In a given 3D stack, these specific features allow the actual process temperature to be elevated in the top-tier layer without introducing any drawback in the bottom-tier one. In addition, short-timescale UV-LA may have some advantages in materials engineering, enabling the nonequilibrium control of certain phenomenon such as crystallization, dopant activation, and diffusion. This paper reviews recent progress reported about the application of short-timescale UV-LA to different stages of CMOS integration, highlighting its potential of being a key enabler for next generation 3D-integrated CMOS devices.

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Variation of Chemical Vapor Deposited SiO₂ Density Due to Generation and Shrinkage of Open Space During Thermal Annealing

Cited by 13 publications

References 15 publications

Origin of Voids at the SiO₂/SiO₂ and SiCN/SiCN Bonding Interface Using Positron Annihilation Spectroscopy and Electron Spin Resonance

Origin of Voids at the SiO₂/SiO₂ and SiCN/SiCN Bonding Interface Using Positron Annihilation Spectroscopy and Electron Spin Resonance

Temporary Direct Bonding by Low Temperature Deposited SiO₂ for Chiplet Applications

Recent Progresses and Perspectives of UV Laser Annealing Technologies for Advanced CMOS Devices

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Variation of Chemical Vapor Deposited SiO2 Density Due to Generation and Shrinkage of Open Space During Thermal Annealing

Cited by 13 publications

References 15 publications

Origin of Voids at the SiO2/SiO2 and SiCN/SiCN Bonding Interface Using Positron Annihilation Spectroscopy and Electron Spin Resonance

Origin of Voids at the SiO2/SiO2 and SiCN/SiCN Bonding Interface Using Positron Annihilation Spectroscopy and Electron Spin Resonance

Temporary Direct Bonding by Low Temperature Deposited SiO2 for Chiplet Applications

Recent Progresses and Perspectives of UV Laser Annealing Technologies for Advanced CMOS Devices

Contact Info

Product

Resources

About

Variation of Chemical Vapor Deposited SiO₂ Density Due to Generation and Shrinkage of Open Space During Thermal Annealing

Origin of Voids at the SiO₂/SiO₂ and SiCN/SiCN Bonding Interface Using Positron Annihilation Spectroscopy and Electron Spin Resonance

Origin of Voids at the SiO₂/SiO₂ and SiCN/SiCN Bonding Interface Using Positron Annihilation Spectroscopy and Electron Spin Resonance

Temporary Direct Bonding by Low Temperature Deposited SiO₂ for Chiplet Applications