In order to evaluate the tip-clearance effect on mixing, 3-D numerical simulations were applied to kneading block section of co-rotating twin screw extruders. The software we used was originally developed for non-Newtonian and non-isothermal flow analysis based on the finite element technique. The marker-particle tracking analysis was also developed in order to estimate the particle path, residence time distribution, stress and strain history, and so on.The stress distribution obtained by the above-mentioned simulations suggested the following mixing mechanisms. The kneading block with the small tip-clearance (TC) caused the bimodal stress distribution which had peaks in both high and low stress level. The marker-particles which overpassed the TC formed the peak at the high stress level and the other particles contributed to the peak at the low stress level. In other words, a large number of particles evaded the TC and it caused heterogeneous stress induced mixing. On the other hand, the large tip-clearance caused the narrow and sharp stress distribution because most of the particles passed over the TC. The stress level was not high, however, homogeneous stress induced mixing was expected. Since the tip-clearance applied a significant effect to the dispersive mixing, it should be optimised in accordance with the material design.

To obtain reliable 3D stacking, a void-free bonding interface should be obtained during wafer-to-wafer direct bonding. Historically, SiO2 is the most studied dielectric layer for direct bonding applications, and it is reported to form voids at the interface. Recently, SiCN has raised as a new candidate for bonding layer. Further understanding of the mechanism behind void formation at the interface would allow to avoid bonding voids on different dielectrics. In this study, the void formation at the bonding interface was studied for a wafer pair of SiO2 and SiCN deposited by plasma enhanced chemical vapor deposition (PECVD). The presence of voids for SiO2 was confirmed after the post-bond anneal (PBA) at 350°C by Scanning Acoustic Microscopy. Alternatively, SiCN deposited by PECVD has demonstrated a void-free interface after post bond annealing. To better understand the mechanism of void formation at the SiO2 bonding interface, we used Positron Annihilation Spectroscopy (PAS) to inspect the atomic-level open spaces and Electron Spin Resonance (ESR) to evaluate the dangling bond formation by N2 plasma activation. By correlating these results with previous results, a model for void formation mechanism at the SiO2 and the absence of for SiCN bonding interface is proposed.

Silicon carbon nitride (SiCN) compounds have aroused great interest as dielectric materials for direct bonding because of the high thermal stability and high bond strength, as well as its Cu diffusion barrier properties. While wafer-to-wafer direct bonding, including the dielectric deposition step, is generally performed at high temperature (>350 °C), applications such as heterogeneous chips and DRAMs would require wafer-to-wafer direct bonding at lower temperature (<250 °C). In this study, we evaluate, for SiCN deposited at various temperatures, the impact for direct wafer bonding of lowering the temperature of all processes. Chemical and mechanical properties of SiCN direct bonding are studied.

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Achieving a void-free bonding interface is an important requirement for the wafer-to-wafer direct bonding process. The two main potential mechanisms for void formation at the interface are (i) void formation induced by gas, such as condensation by-products caused by the bonding process or outgassing of trapped precursors, and (ii) void formation induced by physical obstacles, such as particles. In this work, emphasis is on the latter process. Particles were intentionally deposited on the wafer prior to bonding to study the kinetics of the physical void formation process. Void formations induced by particles deposited on different dielectrics bonding materials were analyzed using scanning acoustic microscopy and image software. The void formation mechanism is then discussed along with the wafer bonding dynamics at room temperature.