Variation resilient low-power memristor-based synchronous flip-flops: design and analysis

IET Circuits, Devices & Systems

Gupta

et al. 2019

Self Cite

Higher variation resilience, lower power consumption, and higher reliability are the three principal design metrics for designing a static random-access memory (SRAM) cell. The most intuitive way to achieve lower power consumption is voltage scaling. However, voltage scaling at nanometre technology nodes leads to degradation in the robustness of the SRAM cell and decreased data stability. It is proved that conventional 6T SRAM fails to maintain its stability in scaled technology, particularly in the deep-subthreshold regime. Furthermore, SRAM cells utilising techniques such as read decoupling, for achieving reliable read operation, tend to increase leakage current resulting in higher hold power, which contributes a major portion to the total power consumption in modern internet of things devices. To cater to the requirements of higher robustness and lower hold power dissipation, a transmission gate-based 9T SRAM is proposed, which achieves these requirements at the cost of slightly higher read and write access time. The simulations are performed utilising a 16-nm complementary metal oxide semiconductor model.

Section: Simulation Results and Discussionmentioning

confidence: 99%

Transmission gate‐based 9T SRAM cell for variation resilient low power and reliable internet of things applications

IET Circuits, Devices & Systems

Gupta

et al. 2019

Self Cite

“…2 (a)) which depicts the change in the amount of current flowing through the memristor with supply voltage across it, due to the change in its resistance. It indicates the ability of such a device to store data in a nonvolatile fashion [5]. The model parameters used in this work are chosen in accordance with [29].…”

Section: Memristor and Its Switching Mechanismmentioning

confidence: 99%

“…Memristor switches between one or more than one value of resistances on application of appropriate voltage levels [5]. Such distinct resistance levels can have one or more discrete values or have a continuous variable resistance.…”

Section: Introductionmentioning

confidence: 99%

Design of Power- and Variability-Aware Nonvolatile RRAM Cell Using Memristor as a Memory Element

IEEE J. Electron Devices Soc.

Bose

et al. 2019

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A 3 CNFETs and 2 memristors-based half-select disturbance free 3T2R resistive RAM (RRAM) cell is proposed in this paper. While the two memristors act as the nonvolatile memory elements, CNFETs are employed as high-performance switches. The proposed cell is capable of implementing bit-interleaving architecture and various error correction coding (ECC) schemes can be applied to mitigate soft-errors. The 3T2R cell has been compared with the standard 6T SRAM (S6T) and 2T2R cells. At a supply voltage of 2 V, the 3T2R cell exhibits 7.24× shorter write delay (T WA ) and 2.89× lower variability in T WA than that of 2T2R. Moreover, it exhibits 5.08 × /4.33× lower variability in T RA and 1.46 × 10 7 × /2.07× lower hold power (H PWR ) dissipation than that of S6T/ 2T2R at V DD = 2 V. In addition, it exhibits tolerance to variations in V th of memristor while being immune to resistance-state drift and random telegraph noise (RTN)-induced instabilities during the read operation. The vastly superior characteristics of CNFET devices over MOSFETs, in combination with memristor technology, leads to such appreciable improvement in design metrics of the proposed design.

“…The resistance change is long‐lasting even after the removal of the electrical field. It implies the retentivity characteristic of the element and hence the cell with such an element behaves like a non‐volatile memory [6]. The state of hysteresis is attained by the memristor when a sufficient amount of charge passes through it so that ions cannot move.…”

Section: Emerging Technologiesmentioning

confidence: 99%

“…Hence, memristive devices are widely used for efficient storage. Other potential applications of memristor are in the neural network [4, 5] and in memory design (flip–flop) [6]. Furthermore, memristors are also used for the implementation of chaotic circuits [7, 8].…”

Section: Introductionmentioning

confidence: 99%

Design and development of memristor‐based RRAM

IET Circuits, Devices & Systems

Gupta

et al. 2019

Self Cite

A power-and variability-aware non-volatile resistive random access memory (RRAM) cell is presented. Non-volatility is achieved due to the use of a memristor as a memory element, which when integrated with a carbon nanotube field-effect transistor (CNFET) helps achieve tremendous robustness against process variation. The half-select issue, inherent in the 2T2M RRAM cell (state-of-the-art design based on the memristor) have been resolved and its circuit parameters have been compared with those of the proposed cell. Also, the proposed cell has been compared with the standard 6T SRAM (S6T) cell. The proposed cell shows 1.6×/4.08× narrower read delay/write delay variability compared with 2T2M. 5CNFET2M also shows 1.8× narrower read delay variability than that of S6T. Furthermore, the proposed cell shows 6.9× shorter write delay in comparison with the 2T2M RRAM cell. 5CNFET2M consumes 10 6 ×/1.34× lower power during hold mode compared with the conventional 6T static random access memory/2T2M RRAM cell. Furthermore, the proposed cell also shows improvement in hold power variability compared with both the cells. All the simulated data, presented here are at the nominal supply voltage of 1 V. These improvements are gained at the expense of slightly longer read time compared with 2T2M/S6T and 31.3× longer write delay compared with S6T.