VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects

Sarangi, Smruti R.; Greskamp, Brian; Teodorescu, Radu; Nakano, Jun; Tiwari, Abhishek; Torrellas, Josep

doi:10.1109/tsm.2007.913186

Cited by 327 publications

(221 citation statements)

References 20 publications

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“…Mesh buffers were simulated using Predictive Technology Model (45 nm PTM HP from [10]). Threshold voltage V th and channel length L eff are the two key device parameters that are subject to variation in DSM technology ( [15]). So we consider only these two variations to incorporate the process variations.…”

Section: Short Circuit (Sc)mentioning

confidence: 99%

Capacitance driven clock mesh synthesis to minimize skew and power dissipation

Reuben

Zackriya.V

Nashit

et al. 2013

IEICE Electron. Express

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Tree driven mesh is gaining popularity as a viable method to distribute clock with minimum skew in Deep Sub Micron (DSM) technology. In the design of the leaf level mesh, the density of the mesh at various parts of the chip is a crucial factor which decides the clock skew and power dissipated in the mesh. We propose a capacitance driven mesh formation methodology which forms a minimum wire length, non-uniform mesh when compared to the traditional skewdriven mesh. After connecting the sinks to the mesh by a combination of Steiner tree and stubs, appropriately sized buffers are placed at optimal locations such that skew and power dissipation are minimized. When our algorithms were tested on ISPD2010 benchmarks, the power dissipated in the mesh was found to be 25% lesser and the skew was 32% to 45% lesser than the skew driven mesh.

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Section: Short Circuit (Sc)mentioning

confidence: 99%

Capacitance driven clock mesh synthesis to minimize skew and power dissipation

Reuben

Zackriya.V

Nashit

et al. 2013

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…Process variation (PV) in IC manufacturing is the deviation of IC parameter values from nominal specifications, due to the nature of the manufacturing process [6][11] [14] It is observed that PV is caused by the inability to precisely control the fabrication process at small-feature technologies [35]. For example, the lithographic lens aberrations result in systematic errors on transistor sizes, and dopant density fluctuations impose random variations on design parameters.…”

Section: Process Variationmentioning

confidence: 99%

Wireless security techniques for coordinated manufacturing and on-line hardware trojan detection

Wei

Potkonjak

2012

Proceedings of the Fifth ACM Conference on Security and Privacy in Wireless and Mobile Networks

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This paper addresses the hardware Trojan (HT) attacks that impose severe threats to the security and integrity of wireless networks and systems. We first develop HT attack models by embedding a single HT gate in the target design that triggers advanced malicious attacks. We place the one-gate HT trigger in such a way that it exhibits rare switching activities, consumes ultra-low leakage power, and hides from delay characterizations. Therefore, the HT attack models are capable of bypassing the widely used side channel-based HT detection schemes. Furthermore, based on the HT attack models, we investigate the potential on-line threat models during the system operation and develop an in-field trusted HT detection approach using physical unclonable functions (PUFs). We evaluate the effectiveness of the HT attack and defense models on a set of ISCAS'85, ISCAS'89, and ITC'99 benchmarks.

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“…There are two parameters that are directly impacted by PV: effective channel length (L) and threshold voltage (V th ) [25]. For V th , we adopt the Gaussian distribution proposed by Asenov et al [26].…”

Section: Preliminaries a Gate Delay Power And Process Variationmentioning

confidence: 99%

Matched public PUF: Ultra low energy security platform

Meguerdichian

Potkonjak

2011

IEEE/ACM International Symposium on Low Power Electronics and Design

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Abstract-Hardware-based physically unclonable functions (PUFs) leverage intrinsic process variation of modern integrated circuits to provide interesting security solutions but either induce high storage requirements or require significant resources of at least one involved party. We use device aging to realize two identical unclonable modules that cannot be matched with any third such module. Each device enables rapid, low-energy computation of ultra-complex functions that are too complex for simulation in any reasonable time. The approach induces negligible area and energy costs and enables a majority of security protocols to be completed in a single or a few clock cycles.

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VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects

Cited by 327 publications

References 20 publications

Capacitance driven clock mesh synthesis to minimize skew and power dissipation

Capacitance driven clock mesh synthesis to minimize skew and power dissipation

Wireless security techniques for coordinated manufacturing and on-line hardware trojan detection

Matched public PUF: Ultra low energy security platform

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