Vector unit architecture for emotion synthesis

Kunimatsu, Atsushi; Ide, N.; Sato, Toshinori; Endo, Yukio; Murakami, Hiroaki; Kamei, T.; Hirano, M.; Ishihara, Fujio; Tago, H.; Oka, Masaaki; Ohba, A.; Tanaka, Yutaka; Okada, Tomoyuki; Suzuoki, M.

doi:10.1109/40.848471

Cited by 26 publications

(11 citation statements)

References 8 publications

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“…Until recently, few of these architectural concepts made it into mainstream processor designs, but the increasingly stringent power/performance requirements for embedded systems have resulted in a number of recent implementations that have adopted these concepts. Chips like the Sony Emotion Engine [23,26,34] and Intel's MXP5800 both achieved high performance at low power by adopting three levels (registers, local memory, external DRAM) of softwaremanaged memory. More recently, the STI Cell processor has adopted a similar approach where data movement between these three address spaces is explicitly controlled by the application.…”

Section: Related Workmentioning

confidence: 99%

Scientific Computing Kernels on the Cell Processor

Williams

Shalf

Oliker

et al. 2007

Int J Parallel Prog

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The slowing pace of commodity microprocessor performance improvements combined with ever-increasing chip power demands has become of utmost concern to computational scientists. As a result, the high performance computing community is examining alternative architectures that address the limitations of modern cache-based designs. In this work, we examine the potential of using the recently-released STI Cell processor as a building block for future high-end computing systems. Our work contains several novel contributions. First, we introduce a performance model for Cell and apply it to several key scientific computing kernels: dense matrix multiply, sparse matrix vector multiply, stencil computations, and 1D/2D FFTs. The difficulty of programming Cell, which requires assembly level intrinsics for the best performance, makes this model useful as an initial step in algorithm design and evaluation. Next, we validate the accuracy of our model by comparing results against published hardware results, as well as our own implementations on a 3.2GHz Cell blade. Additionally, we compare Cell performance to benchmarks run on leading superscalar (AMD Opteron), VLIW (Intel Itanium2), and vector (Cray X1E) architectures. Our work also explores several different mappings of the kernels and demonstrates a simple and effective programming model for Cell's unique architecture. Finally, we propose modest microarchitectural modifications that could significantly increase the efficiency of double-precision calculations. Overall results demonstrate the tremendous potential of the Cell architecture for scientific computations in terms of both raw performance and power efficiency.

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Section: Related Workmentioning

confidence: 99%

Scientific Computing Kernels on the Cell Processor

Williams

Shalf

Oliker

et al. 2007

Int J Parallel Prog

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“…Motorola's AltiVec [9] delivers the full 4-wide SIMD performance. Sony's Emotion Engine [16] has two 4-wide SIMD processors. The first is interfaced to the main CPU as a coprocessor, executing instructions directly from the application's instruction stream.…”

Section: Previous Workmentioning

confidence: 99%

A user-programmable vertex engine

Lindholm

Kilgard

Moreton

2001

Proceedings of the 28th Annual Conference on Computer Graphics and Interactive Techniques

220

125

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In this paper we describe the design, programming interface, and implementation of a very efficient user-programmable vertex engine. The vertex engine of NVIDIA's GeForce3 GPU evolved from a highly tuned fixed-function pipeline requiring considerable knowledge to program. Programs operate only on a stream of independent vertices traversing the pipe. Embedded in the broader fixed function pipeline, our approach preserves parallelism sacrificed by previous approaches. The programmer is presented with a straightforward programming model, which is supported by transparent multi-threading and bypassing to preserve parallelism and performance.In the remainder of the paper we discuss the motivation behind our design and contrast it with previous work. We present the programming model, the instruction set selection process, and details of the hardware implementation. Finally, we discuss important API design issues encountered when creating an interface to such a device. We close with thoughts about the future of programmable graphics devices.

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“…Continuously increasing latency and throughput requirements for many scientific applications motivate the development of hardware methods for high-speed function approximation. Furthermore, correct and efficient hardware computation of elementary functions is necessary in platforms such as graphics processing units (GPUs), digital signal processors (DSPs), floating-point units (FPUs) in general-purpose processors, and application-specific integrated circuits (ASICs) [5][6][7].…”

Section: Introductionmentioning

confidence: 99%

Optimized Linear, Quadratic and Cubic Interpolators for Elementary Function Hardware Implementations

2016

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This paper presents a method for designing linear, quadratic and cubic interpolators that compute elementary functions using truncated multipliers, squarers and cubers. Initial coefficient values are obtained using a Chebyshev series approximation. A direct search algorithm is then used to optimize the quantized coefficient values to meet a user-specified error constraint. The algorithm minimizes coefficient lengths to reduce lookup table requirements, maximizes the number of truncated columns to reduce the area, delay and power of the arithmetic units, and minimizes the maximum absolute error of the interpolator output. The method can be used to design interpolators to approximate any function to a user-specified accuracy, up to and beyond 53-bits of precision (e.g., IEEE double precision significand). Linear, quadratic and cubic interpolator designs that approximate reciprocal, square root, reciprocal square root and sine are presented and analyzed. Area, delay and power estimates are given for 16, 24 and 32-bit interpolators that compute the reciprocal function, targeting a 65 nm CMOS technology from IBM. Results indicate the proposed method uses smaller arithmetic units and has reduced lookup table sizes compared to previously proposed methods. The method can be used to optimize coefficients in other systems while accounting for coefficient quantization as well as truncation and rounding effects of multiple arithmetic units.

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Vector unit architecture for emotion synthesis

Cited by 26 publications

References 8 publications

Scientific Computing Kernels on the Cell Processor

Scientific Computing Kernels on the Cell Processor

A user-programmable vertex engine

Optimized Linear, Quadratic and Cubic Interpolators for Elementary Function Hardware Implementations

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