Vectorless analysis of supply noise induced delay variation

Abstract

The impact of power supply integrity on a design has become a critical issue, not only for functional verification, but also for performance verification. Traditional analysis has typically applied a worst case voltage drop at all points along a circuit path which leads to a very conservative analysis. We also show that in certain cases, the traditional analysis can be optimistic, since it ignores the possibility of voltage shifts between driver and receiver gates. In this paper, we propose a new analysis approach for computing the maximum path delay under power supply fluctuations. Our analysis is based on the use of superposition, both spatially across different circuit blocks, and temporally in time. We first present an accurate model of path delay variations under supply drops, considering both the effect of local supply reduction at individual gates and voltage shifts between driver/receiver pairs. We then formulate the path delay maximization problem as a constrained linear optimization problem, considering the effect of both IR drop and LdI/dt drops. We show how correlations between currents of different circuit blocks can be incorporated in this formulation using linear constraints. The proposed methods were implemented and tested on benchmark circuits, including an industrial power supply grid and we demonstrate a significant improvement in the worst-case path delay increase.

Power distribution network generation for optimizing IR-drop aware timing

“…In general, the larger the voltage at a cell is, the smaller the delay it has. Because the exact voltages at most cells are larger than the applied value, the conventional timing report is usually too pessimistic and this design methodology usually leads to over-design [17] [1]. In certain situations, this design methodology might even underestimate the worst-case delay because it ignores the impact of voltage shifts between driverreceiver pairs [10].…”

“…To reflect the realistic timing of a circuit, IR-drop aware timing analysis should be applied for timing signoff so that the impact of different IR-drops at cells can be simultaneously considered. IRdrop aware timing analysis has been promoted by several publications such as [17] [9] [12] and currently supported by commercial timing-analysis tools. Regarding PDN design, several techniques such as [16] [7] [11] were proposed to speed up the IR-drop analysis by random-walk method [16], preconditioned krylov-subspace iterative method [7], or utilizing the locality of the PDN [11].…”

IR Drop and Ground Bounce Awareness Timing Model

“…The following table shows the significant increase of delay due to IR drop in a 0.13µm technology design, in which Vdd is 1.35V . In modern IC designs, it is important to capture the effect of IR drop and ground bounce efficiently and accurately in order to improve circuit reliability [1,2,3]. Traditionally, there exist two methods which can calculate the variance of delay and output transition time induced by IR drop and ground bounce.…”