Verification of a multiprocessor cache protocol using simulation relations and higher-order logic

Loewenstein, Paul; Dill, David L.

doi:10.1007/bf00709156

Cited by 15 publications

(6 citation statements)

References 7 publications

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“…Several proofs of SC for parameterized protocols are manual in nature. Some [21,26,3] use theorem-provers, while others use formal frameworks to provide a rigorous proof [24]. In either case, a human must develop insights needed to build up the proof, and the process is quite time-consuming.…”

Section: Related Workmentioning

confidence: 99%

Automatic Verification of Sequential Consistency for Unbounded Addresses and Data Values

Bingham

Condon

et al. 2004

Computer Aided Verification

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Sequential consistency is the archetypal correctness condition for the memory protocols of shared-memory multiprocessors. Typically, such protocols are parameterized by the number of processors, the number of addresses, and the number of distinguishable data values, and typically, automatic protocol verification analyzes only concrete instances of the protocol with small values (generally < 3) for the protocol parameters. This paper presents a fully automatic method for proving the sequential consistency of an entire parameterized family of protocols, with the number of processors fixed, but the number of addresses and data values being unbounded parameters. Using some practical, reasonable assumptions (data independence, processor symmetry, location symmetry, simple store ordering, some syntactic restrictions), the method automatically generates a finite-state abstract protocol from the parameterized protocol description; proving sequential consistency of the abstract model, via known methods, guarantees sequential consistency of the entire protocol family. The method is sound, but incomplete, but we argue that it is likely to apply to most real protocols. We present experimental results showing the effectiveness of our method on parameterized versions of the Piranha shared memory protocol and an extended version of a directory protocol from the University of Wisconsin Multifacet Project.

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Section: Related Workmentioning

confidence: 99%

Automatic Verification of Sequential Consistency for Unbounded Addresses and Data Values

Bingham

Condon

et al. 2004

Computer Aided Verification

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“…Another technique for validating protocols relies on logical proofs [5,15,20]. This approach can validate a full range of properties.…”

Section: Current Approachesmentioning

confidence: 99%

A new approach for the verification of cache coherence protocols

Pong

Dubois

1995

IEEE Trans. Parallel Distrib. Syst.

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In this paper, we introduce a cache protocol verification technique based on a symbolic state expansion procedure. A global FSM (Finite State Machine) model characterizing the protocol behavior is built and protocol verification becomes equivalent to finding whether or not the global FSM may enter erroneous states. In order to reduce the complexity of the state expansion process, all the caches in the same state are grouped into an equivalence class and the number of caches in the class is symbolically represented by a repetition constructor. This symbolic representation is partly justified by the symmetry and homogeneity of cache-based systems. However, the key idea behind the representation is to exploit a unique property of cache coherence protocols: the fact that protocol correctness is not dependent on the exact number of cached copies. Rather, symbolic states only need to keep track of whether the caches have 0, 1 or multiple copies. The resulting symbolic state expansion process only takes a few steps and verifies the protocol for any system size. Therefore, it is more efficient and reliable than current approaches. The verification procedure is first applied to the verification of five existing protocols under the assumption of atomic protocol transitions. A simple snooping protocol on a split-transaction shared bus is also verified to illustrate the extension of our approach to protocols with non-atomic transitions.

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“…The details and complications of this approach are beyond the scope of this paper, and the reader is referred to [20,21,10,1] for them. Following the approach in [1,21,20,16] 3 the proof of correctness makes use of an abstraction function that maps an implementation state into a corresponding specification state. Correctness can then be reduced to showing that for any execution trace of the implementation machine there exists a corresponding execution trace of the specification machine.…”

Section: Microprocessor Correctnessmentioning

confidence: 99%

Ground temporal logic: A logic for hardware verification

Cyrluk

Narendran

1994

Computer Aided Verification

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We present a new temporal logic, GTL, appropriate for specifying properties of hardware at the register transfer level. We argue that this logic represents an improvement over model checking for some natural hardware verification problems. We show that the validity problem for this logic is //11 complete. We then identify a fragment of the logic that is decidable. We show that in this fragment we are still able to encode many interesting problems, including the correctness of pipelined microprocessors.

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Verification of a multiprocessor cache protocol using simulation relations and higher-order logic

Cited by 15 publications

References 7 publications

Automatic Verification of Sequential Consistency for Unbounded Addresses and Data Values

Automatic Verification of Sequential Consistency for Unbounded Addresses and Data Values

A new approach for the verification of cache coherence protocols

Ground temporal logic: A logic for hardware verification

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