Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets

In today's systems, analog and mixed-signal (AMS) circuits are tightly interwoven with HW/SW systems and the application. Hence, a verification of the AMS part alone is not sufficient any more, in particular considering its application in Cyber-Physical Systems. In order to guarantee 'first time right', the accuracy of the models, the validation of the application fitness, and in changing, uncertain environments will become at least as important. In this paper we discuss and give an overview of methods that strive for validation of AMS systems with increased coverage. We in particular focus modeling, verification and validation of uncertainties in the context of Cyber-Physical Systems.

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“…[47]). [47] translates a subset of VHDL-AMS to labeled hybrid Petri nets, on which formal methods are applied.…”

Section: A Ability To Integrate In Design Flowsmentioning

confidence: 93%

“…Tools for translation are not provided (as in [35], [40], [45], [46]), or only for a subset (e.g. [47]). [47] translates a subset of VHDL-AMS to labeled hybrid Petri nets, on which formal methods are applied.…”

Section: A Ability To Integrate In Design Flowsmentioning

confidence: 99%

Verification and validation of AMS systems: Towards coverage of uncertainties

Grimm

Radojicic

2015

2015 IEEE 20th International Mixed-Signals Testing Workshop (IMSTW)

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“…The nominal values of the inductor L and the capacitor C are 2µH and 10µF, respectively. We assume that L and C are independent random variables uniformly distributed in the range L ∈ [1.8, 2.2]µH and C ∈ [9,11]µF.…”

Section: A Problem Setupmentioning

confidence: 99%

“…In the series of papers by Myers et al [9], [10], labeled hybrid Petri nets were used to formalize and model check circuits. However, their techniques mostly focus on the behavioral models of analog circuits.…”

Section: A Related Workmentioning

confidence: 99%

From statistical model checking to statistical model inference: Characterizing the effect of process variations in analog circuits

Zhang

Sankaranarayanan

Somenzi

et al. 2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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This paper studies the effect of parameter variation on the behavior of analog circuits at the transistor (netlist) level. It is well known that variation in key circuit parameters can often adversely impact the correctness and performance of analog circuits during fabrication. An important problem lies in characterizing a safe subset of the parameter space for which the circuit can be guaranteed to satisfy the design specification. Due to the sheer size and complexity of analog circuits, a formal approach to the problem remains out of reach, especially at the transistor level. Therefore, we present a statistical model inference approach that exploits recent advances in statistical verification techniques. Our approach uses extensive circuit simulations to infer polynomials that approximate the behavior of a circuit. A procedure inspired by statistical model checking is then introduced to produce "statistically sound" models that extend the polynomial approximation. The resulting model can be viewed as a statistically guaranteed over-approximation of the circuit behavior. The proposed technique is demonstrated with two case studies in which it identifies subsets of parameters that satisfy the design specifications.

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“…An adaptation of formalisms based on temporal logics and regular expressions to the needs of the hardware industry has been done through standard specification languages PSL [12] and SVA [2]. Similar verification methods have been introduced in the analog and mixed-signal domain with the advent of hybrid automata [19] and hybrid Petri-nets [18], which serve as models to describe systems with continuous dynamics with switches, and the algorithms for the exhaustive exploration of their search space. While certain progress has been made recently in that field [3,13], scalability remains an important issue for the exhaustive verification of hybrid systems, due to the explosion of the underlying state space.…”

Section: Introductionmentioning

confidence: 99%

Analog property checkers: a DDR2 case study

Jones

Konrad

Ničković

2009

Form Methods Syst Des

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The formal specification component of verification can be exported to simulation through the idea of property checkers. The essence of this approach is the automatic construction of an observer from the specification in the form of a program that can be interfaced with a simulator and alert the user if the property is violated by a simulation trace. Although not complete, this lighter approach to formal verification has been effectively used in software and digital hardware to detect errors. Recently, the idea of property checkers has been extended to analog and mixed-signal systems.In this paper, we apply the property-based checking methodology to an industrial and realistic example of a DDR2 memory interface. The properties describing the DDR2 analog behavior are expressed in the formal specification language STL/PSL in form of assertions. The simulation traces generated from an actual DDR2 interface design are checked with respect to the STL/PSL assertions using the AMT tool. The focus of this paper is on the translation of the official (informal and descriptive) specification of two non-trivial DDR2 properties into STL/PSL assertions. We study both the benefits and the current limits of such approach.

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Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets

Cited by 18 publications

References 19 publications

Verification and validation of AMS systems: Towards coverage of uncertainties

Verification and validation of AMS systems: Towards coverage of uncertainties

From statistical model checking to statistical model inference: Characterizing the effect of process variations in analog circuits

Analog property checkers: a DDR2 case study

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