Verification of configurable processor cores

Puig-Medina, Marinés; Ezer, G.; Konas, Pavlos

doi:10.1145/337292.337527

Cited by 20 publications

(8 citation statements)

References 9 publications

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“…Functional verification of a reconfigurable processor is still an unexplored research area, though high-level processor verification [129][130][131] is relatively well studied. This is expected since options for detailed design exploration are absent in the state of the art for reconfigurable processors.…”

Section: Performance Estimation and Verificationmentioning

confidence: 99%

Ingredients of Adaptability: A Survey of Reconfigurable Processors

Chattopadhyay

2013

VLSI Design

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For a design to survive unforeseen physical effects like aging, temperature variation, and/or emergence of new application standards, adaptability needs to be supported. Adaptability, in its complete strength, is present in reconfigurable processors, which makes it an important IP in modern System-on-Chips (SoCs). Reconfigurable processors have risen to prominence as a dominant computing platform across embedded, general-purpose, and high-performance application domains during the last decade. Significant advances have been made in many areas such as, identifying the advantages of reconfigurable platforms, their modeling, implementation flow and finally towards early commercial acceptance. This paper reviews these progresses from various perspectives with particular emphasis on fundamental challenges and their solutions. Empowered with the analysis of past, the future research roadmap is proposed.

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Section: Performance Estimation and Verificationmentioning

confidence: 99%

Ingredients of Adaptability: A Survey of Reconfigurable Processors

Chattopadhyay

2013

VLSI Design

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“…Tensilica provides support for XTensa in terms of compilation, synthesis, and verification [21]. Embedded designers use these tools by providing a high level specification for a processor core.…”

Section: Design Navigationmentioning

confidence: 99%

Balancing design options with Sherpa

Sherwood

Oskin

Calder

2004

Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems

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Application specific processors offer the potential of rapidly designed logic specifically constructed to meet the performance and area demands of the task at hand. Recently, there have been several major projects that attempt to automate the process of transforming a predetermined processor configuration into a low level description for fabrication. These projects either leave the specification of the processor to the designer, which can be a significant engineering burden, or handle it in a fully automated fashion, which completely removes the designer from the loop.In this paper we introduce a technique for guiding the design and optimization of application specific processors. The goal of the Sherpa design framework is to automate certain design tasks and provide early feedback to help the designer navigate their way through the architecture design space. Our approach is to decompose the overall problem of choosing an optimal architecture into a set of sub-problems that are, to the first order, independent. For each sub-problem, we create a model that relates performance to area. From this, we build a constraint system that can be solved using integer-linear programming techniques, and arrive at an ideal parameter selection for all architectural components. Our approach only takes a few minutes to explore the design space allowing the designer or compiler to see the potential benefits of optimizations rapidly. We show that the expected performance using our model correlates strongly to detailed pipeline simulations, and present results showing design tradeoffs for several different benchmarks.

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“…To justify the cost of developing and evaluating an application-specific fault model, the market for the application must be very large and the fault modes of the application must be well understood. For this reason, application-specific fault models are seen in microprocessor test and validation [26,27,28,29,30,31]. Early microprocessor fault models target relatively generic microprocessor features.…”

Section: Application-specific Fault Modelsmentioning

confidence: 99%

Fault models and test generation for hardware-software covalidation

Harris

2003

IEEE Des. Test. Comput.

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The increasing use of hardware-software systems in cost-critical and life-critical applications has led to heightened significance of design correctness of these systems. This article presents a summary of research in test generation and fault models to support hardware-software covalidation. The covalidation problem involves the verification of design correctness using simulation-based techniques. The article focuses on the test generation process for hardware-software systems and the fault models which support test generation.

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Verification of configurable processor cores

Cited by 20 publications

References 9 publications

Ingredients of Adaptability: A Survey of Reconfigurable Processors

Ingredients of Adaptability: A Survey of Reconfigurable Processors

Balancing design options with Sherpa

Fault models and test generation for hardware-software covalidation

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