This paper presents a verification methodology for configurable processor cores. The simulation-based approach uses directed diagnostics and pseudo-random program generators both of which are tailored to specific processor instances. A configurable and extensible test-bench serves as the framework for the verification process and offers components necessary for the complete SOC verification. Coverage analysis provides an evaluation of how well a specific design has been exercised, of the breadth of the configuration space explored, and suggests improvements to the process. The results of the analysis show that our methodology achieves good verification coverage of the processor implementation.

This paper describes the third generation configurable and extensible XtensaTM processor with enhanced DSP functionali9 targeted to System-On-Chip (SOC) designs. Xtensa I l l processor family can be configured with an IEEE-compatible Boating point unit (FPU) andlor a powerful, energy eficient Vector Integer coprocessor, both implemented using Tensilica Instruction Extension (TIE) language and automatically integrated with the Xtensa base processor core.

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Unifiing the integer ana' floating-point datapath of the R4200 MIPS microprocessor allows for the sharing of some of the major hardware resources within the integer ana'poating-point execution units, and simpl@es a large portion of the peripheral circuitry. The uniJied datapath results in a more eficient use of hardware with reduced average power dissipation, area and development time, without compromising the major performance advantages of RISC processors.

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